esl-epfl / x-heepLinks
eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
☆186Updated this week
Alternatives and similar repositories for x-heep
Users that are interested in x-heep are comparing it to the libraries listed below
Sorting:
- A Fast, Low-Overhead On-chip Network☆207Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆257Updated 2 weeks ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆110Updated 2 weeks ago
- Vector processor for RISC-V vector ISA☆119Updated 4 years ago
- SystemVerilog synthesis tool☆194Updated 2 months ago
- A dynamic verification library for Chisel.☆151Updated 6 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 6 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆263Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆160Updated last week
- An energy-efficient RISC-V floating-point compute cluster.☆84Updated this week
- RISC-V Verification Interface☆92Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆135Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆238Updated 7 months ago
- A Chisel RTL generator for network-on-chip interconnects☆198Updated 3 weeks ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆159Updated last week
- Verilog Configurable Cache☆178Updated 6 months ago
- Generic Register Interface (contains various adapters)☆120Updated 8 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆500Updated 3 months ago
- VeeR EL2 Core☆278Updated 2 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆77Updated this week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- Basic RISC-V Test SoC☆128Updated 6 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆156Updated 3 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated 3 weeks ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆177Updated 5 years ago
- RISC-V microcontroller IP core developed in Verilog☆173Updated last month
- (System)Verilog to Chisel translator☆114Updated 3 years ago
- Fabric generator and CAD tools.☆185Updated last week
- RISC-V System on Chip Template☆158Updated last week