esl-epfl / x-heep
eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
☆165Updated this week
Alternatives and similar repositories for x-heep:
Users that are interested in x-heep are comparing it to the libraries listed below
- A Fast, Low-Overhead On-chip Network☆178Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆245Updated 2 weeks ago
- Verilog Configurable Cache☆171Updated 3 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆64Updated last month
- RISC-V Verification Interface☆84Updated last week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆162Updated 3 months ago
- A dynamic verification library for Chisel.☆146Updated 3 months ago
- Generic Register Interface (contains various adapters)☆109Updated 5 months ago
- RISC-V System on Chip Template☆156Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆229Updated this week
- Unit tests generator for RVV 1.0☆76Updated 3 weeks ago
- SystemVerilog synthesis tool☆179Updated this week
- Vector processor for RISC-V vector ISA☆113Updated 4 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆225Updated 3 months ago
- RISC-V Torture Test☆182Updated 7 months ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆133Updated 5 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- VeeR EL2 Core☆265Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆183Updated 3 months ago
- Fabric generator and CAD tools☆162Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆123Updated this week
- Instruction Set Generator initially contributed by Futurewei☆272Updated last year
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆264Updated this week
- A demo system for Ibex including debug support and some peripherals☆62Updated 6 months ago
- ☆88Updated last year
- WAL enables programmable waveform analysis.☆146Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆71Updated 11 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆145Updated 2 weeks ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆172Updated last year