esl-epfl / x-heepLinks
eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
☆217Updated last week
Alternatives and similar repositories for x-heep
Users that are interested in x-heep are comparing it to the libraries listed below
Sorting:
- A Fast, Low-Overhead On-chip Network☆231Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆291Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆92Updated 2 months ago
- RISC-V Verification Interface☆108Updated this week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 11 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆145Updated 3 weeks ago
- Vector processor for RISC-V vector ISA☆129Updated 5 years ago
- Verilog Configurable Cache☆184Updated 2 weeks ago
- RISC-V System on Chip Template☆159Updated 2 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆184Updated last month
- A Chisel RTL generator for network-on-chip interconnects☆215Updated 2 months ago
- ☆298Updated last month
- Tile based architecture designed for computing efficiency, scalability and generality☆272Updated last month
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆122Updated last week
- A dynamic verification library for Chisel.☆156Updated 11 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆142Updated 2 weeks ago
- SystemVerilog synthesis tool☆216Updated 7 months ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆387Updated last week
- Network on Chip Implementation written in SytemVerilog☆192Updated 3 years ago
- ASIC implementation flow infrastructure☆143Updated this week
- Generic Register Interface (contains various adapters)☆130Updated 2 weeks ago
- ☆99Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆271Updated 2 weeks ago
- ☆149Updated 2 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆299Updated 2 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆158Updated 3 weeks ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- An energy-efficient RISC-V floating-point compute cluster.☆113Updated last week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago