Alternatives and similar repositories for x-heep

Users that are interested in x-heep are comparing it to the libraries listed below

• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆211Updated last week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆261Updated last week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆202Updated last month
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆268Updated this week
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆121Updated 4 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆178Updated 6 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆165Updated this week
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆178Updated 2 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆113Updated this week
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆166Updated 7 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆121Updated last week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆67Updated last year
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆198Updated 3 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆84Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆504Updated 4 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆136Updated this week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 7 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆237Updated 7 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆112Updated last week
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆157Updated last week
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆282Updated last month
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆163Updated last week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆288Updated 2 weeks ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆274Updated 4 months ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆88Updated last week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆101Updated last week
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆126Updated 7 years ago
• SpinalHDL / NaxRiscv
  ☆289Updated 3 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆67Updated 6 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆289Updated last year