Alternatives and similar repositories for openocd_riscv

Users that are interested in openocd_riscv are comparing it to the libraries listed below

• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 6 months ago
• ldoolitt / vhd2vl
  ☆137Updated 9 months ago
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆83Updated last week
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆95Updated 5 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆95Updated this week
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 7 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 4 months ago
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆88Updated 2 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆106Updated 3 weeks ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆118Updated last year
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆91Updated 7 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆97Updated last year
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆78Updated 2 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆88Updated 2 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆125Updated 4 months ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆180Updated last year
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 3 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆80Updated 5 years ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 2 months ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆67Updated 8 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆160Updated 6 months ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆61Updated last week
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated this week