SpinalHDL / openocd_riscv
Spen's Official OpenOCD Mirror
☆48Updated 10 months ago
Alternatives and similar repositories for openocd_riscv:
Users that are interested in openocd_riscv are comparing it to the libraries listed below
- SoftCPU/SoC engine-V☆54Updated last year
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆67Updated this week
- Wishbone interconnect utilities☆38Updated 7 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆74Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆64Updated 9 months ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago
- ☆26Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆86Updated 4 years ago
- FuseSoC standard core library☆124Updated 3 weeks ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- Yet Another RISC-V Implementation☆86Updated 3 months ago
- Naive Educational RISC V processor☆77Updated 3 months ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Wishbone to AXI bridge (VHDL)☆40Updated 5 years ago
- A simple three-stage RISC-V CPU☆22Updated 3 years ago
- TCP/IP controlled VPI JTAG Interface.☆63Updated this week
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆58Updated 6 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 7 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆43Updated 2 months ago
- RISCV model for Verilator/FPGA targets☆49Updated 5 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆72Updated 9 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆83Updated 6 years ago
- Soft-microcontroller implementation of an ARM Cortex-M0☆24Updated 5 years ago
- Reusable Verilog 2005 components for FPGA designs☆39Updated last year
- ☆33Updated 2 years ago
- JTAG DPI module for OpenRISC simulation with Verilator☆17Updated 12 years ago
- PicoRV☆44Updated 4 years ago
- Extensible FPGA control platform☆55Updated last year