SpinalHDL / openocd_riscv
Spen's Official OpenOCD Mirror
☆47Updated 8 months ago
Related projects ⓘ
Alternatives and complementary repositories for openocd_riscv
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆62Updated this week
- SoftCPU/SoC engine-V☆54Updated last year
- Wishbone interconnect utilities☆36Updated 5 months ago
- FuseSoC standard core library☆112Updated 3 weeks ago
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- Naive Educational RISC V processor☆71Updated 3 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Bitstream relocation and manipulation tool.☆39Updated last year
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆41Updated 2 weeks ago
- ☆36Updated 2 years ago
- Featherweight RISC-V implementation☆52Updated 2 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆78Updated 4 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆36Updated 9 months ago
- ☆26Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆60Updated 7 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆35Updated last year
- Repo that shows how to use the VexRiscv with OpenOCD and semihosting.☆21Updated 2 years ago
- ☆57Updated 3 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated 10 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆57Updated 2 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆85Updated 4 years ago
- Platform Level Interrupt Controller☆35Updated 6 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆63Updated 2 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆64Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆36Updated last year
- ☆34Updated 9 months ago
- Extensible FPGA control platform☆53Updated last year
- RISCV model for Verilator/FPGA targets☆44Updated 5 years ago
- RISC-V Nox core☆61Updated 3 months ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆62Updated this week