lowRISC / epic-c-exampleLinks
ePIC (Embedded PIC) example: kernel and relocatable loadable app
☆14Updated last year
Alternatives and similar repositories for epic-c-example
Users that are interested in epic-c-example are comparing it to the libraries listed below
Sorting:
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆57Updated last month
- 📦 Prebuilt RISC-V GCC toolchains for x64 Linux.☆104Updated 7 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆27Updated 4 years ago
- ☆147Updated 2 years ago
- HW Design Collateral for Caliptra RoT IP☆112Updated this week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated 11 months ago
- RISC-V Core Local Interrupt Controller (CLINT)☆28Updated 3 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago
- UNSUPPORTED INTERNAL toolchain builds☆46Updated last week
- ☆42Updated 3 years ago
- ☆89Updated last month
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- RISC-V Verification Interface☆107Updated 3 weeks ago
- ☆190Updated last year
- RISC-V System on Chip Template☆159Updated last month
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆38Updated 2 months ago
- RISC-V Nox core☆68Updated 2 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 11 months ago
- The multi-core cluster of a PULP system.☆108Updated 2 weeks ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- RISC-V microcontroller IP core developed in Verilog☆183Updated 6 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- Verilog implementation of a RISC-V core☆125Updated 7 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆244Updated 11 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆102Updated 4 years ago
- ☆108Updated 2 months ago
- RISC-V IOMMU Specification☆136Updated 2 weeks ago