Alternatives and similar repositories for clic

Users that are interested in clic are comparing it to the libraries listed below

• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆85Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 6 months ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆101Updated 5 months ago
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆20Updated 2 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆192Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆82Updated 3 years ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆160Updated 5 months ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆128Updated last week
• chipsalliance / VeeR-ISS
  ☆151Updated 2 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆73Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆135Updated this week
• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆100Updated 7 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆258Updated 3 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆195Updated last month
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆315Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆225Updated 10 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆170Updated 6 years ago
• chipsalliance / uvm-verilator
  ☆113Updated 2 months ago
• pulp-platform / pulp-sdk
  ☆123Updated 2 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆148Updated 3 weeks ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆128Updated 8 months ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆186Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆78Updated last month
• jamieiles / uart
  Verilog UART
  ☆191Updated 12 years ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 6 months ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆57Updated this week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆79Updated 2 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆95Updated last month
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆121Updated 4 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆291Updated last month