pulp-platform / clicLinks
RISC-V fast interrupt controller
☆28Updated 2 months ago
Alternatives and similar repositories for clic
Users that are interested in clic are comparing it to the libraries listed below
Sorting:
- A demo system for Ibex including debug support and some peripherals☆76Updated 3 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated 2 months ago
- ☆94Updated last month
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- HW Design Collateral for Caliptra RoT IP☆111Updated this week
- ☆187Updated last year
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆124Updated 4 months ago
- CVA6 SDK containing RISC-V tools and Buildroot☆74Updated 2 months ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 2 months ago
- ☆97Updated 2 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 2 months ago
- ☆244Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆175Updated 10 months ago
- ☆145Updated last year
- RISC-V Verification Interface☆103Updated 3 months ago
- RISC-V Torture Test☆197Updated last year
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆113Updated last week
- ☆90Updated 3 weeks ago
- RISC-V Nexus Trace TG documentation and reference code☆52Updated 8 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆137Updated last month
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- RISC-V Nox core☆68Updated 2 months ago
- A Fast, Low-Overhead On-chip Network☆226Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆183Updated last week
- VeeR EL2 Core☆298Updated last week
- RISC-V System on Chip Template☆159Updated last month
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- open-source Ethenet media access controller for Ariane on Genesys-2☆19Updated 6 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆90Updated last month