pulp-platform / clicLinks
RISC-V fast interrupt controller
☆26Updated last month
Alternatives and similar repositories for clic
Users that are interested in clic are comparing it to the libraries listed below
Sorting:
- A demo system for Ibex including debug support and some peripherals☆73Updated 2 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated last month
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆128Updated 2 weeks ago
- ☆182Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- ☆90Updated last week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆173Updated 8 months ago
- ☆241Updated 2 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last month
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆185Updated 3 weeks ago
- RISC-V System on Chip Template☆159Updated last week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆275Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated 3 weeks ago
- A Fast, Low-Overhead On-chip Network☆220Updated last week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆218Updated 4 years ago
- RISC-V Verification Interface☆100Updated 2 months ago
- HW Design Collateral for Caliptra RoT IP☆107Updated this week
- ☆97Updated last year
- Basic RISC-V Test SoC☆139Updated 6 years ago
- ☆141Updated last year
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆205Updated last week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆138Updated 3 weeks ago
- ☆115Updated 2 weeks ago
- VeeR EL2 Core☆293Updated this week
- SystemVerilog synthesis tool☆207Updated 5 months ago
- ☆293Updated last month
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆123Updated 2 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆103Updated last year
- RISC-V Virtual Prototype☆172Updated 8 months ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 5 years ago