pulp-platform / clicLinks
RISC-V fast interrupt controller
☆29Updated 3 weeks ago
Alternatives and similar repositories for clic
Users that are interested in clic are comparing it to the libraries listed below
Sorting:
- A demo system for Ibex including debug support and some peripherals☆84Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- RISC-V System on Chip Template☆159Updated 3 months ago
- ☆97Updated 3 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆169Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated last month
- ☆110Updated last month
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆118Updated 4 years ago
- Basic RISC-V Test SoC☆162Updated 6 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated last month
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆98Updated 5 months ago
- ☆150Updated 2 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆127Updated 7 months ago
- RISC-V Nox core☆70Updated 4 months ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆127Updated 2 weeks ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆71Updated last year
- My notes for DDR3 SDRAM controller☆42Updated 2 years ago
- open-source Ethenet media access controller for Ariane on Genesys-2☆19Updated 6 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆221Updated 5 years ago
- HW Design Collateral for Caliptra RoT IP☆123Updated this week
- ☆190Updated 2 years ago
- SystemVerilog synthesis tool☆220Updated 9 months ago
- Arduino compatible Risc-V Based SOC☆158Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆76Updated 3 years ago
- RISC-V Verification Interface☆129Updated this week
- AHB3-Lite Interconnect☆107Updated last year
- Control and status register code generator toolchain☆156Updated 2 weeks ago
- RISC-V Debug Support for our PULP RISC-V Cores☆288Updated 3 weeks ago