pulp-platform / clic
RISC-V fast interrupt controller
☆24Updated last month
Alternatives and similar repositories for clic:
Users that are interested in clic are comparing it to the libraries listed below
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆98Updated last month
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆56Updated 3 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 2 months ago
- A demo system for Ibex including debug support and some peripherals☆63Updated last week
- The multi-core cluster of a PULP system.☆91Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 6 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆72Updated 3 weeks ago
- Open-source high performance AXI4-based HyperRAM memory controller☆74Updated 2 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated 2 months ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆91Updated last month
- ☆86Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆63Updated 11 months ago
- Naive Educational RISC V processor☆83Updated 6 months ago
- Simple runtime for Pulp platforms☆47Updated last month
- RISC-V Nox core☆62Updated last month
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 5 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 9 months ago
- CVA6 SDK containing RISC-V tools and Buildroot☆65Updated 10 months ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- RISCV model for Verilator/FPGA targets☆51Updated 5 years ago
- ☆92Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆41Updated 2 years ago
- Platform Level Interrupt Controller☆40Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- RISC-V Verification Interface☆89Updated 2 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆31Updated last year
- HW Design Collateral for Caliptra RoT IP☆90Updated last week
- My notes for DDR3 SDRAM controller☆33Updated 2 years ago