pulp-platform / clicLinks
RISC-V fast interrupt controller
☆24Updated last month
Alternatives and similar repositories for clic
Users that are interested in clic are comparing it to the libraries listed below
Sorting:
- A demo system for Ibex including debug support and some peripherals☆67Updated last week
- The multi-core cluster of a PULP system.☆97Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated 2 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 3 months ago
- ☆95Updated last year
- Naive Educational RISC V processor☆83Updated 7 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆47Updated 7 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆103Updated last week
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆94Updated 2 months ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 6 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 10 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆31Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆89Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆77Updated this week
- HW Design Collateral for Caliptra RoT IP☆93Updated this week
- RISC-V Nox core☆62Updated 2 months ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆76Updated last week
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆43Updated last month
- pulp_soc is the core building component of PULP based SoCs☆79Updated 2 months ago
- My notes for DDR3 SDRAM controller☆35Updated 2 years ago
- BlackParrot on Zynq☆41Updated 2 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆98Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated 3 weeks ago
- RISC-V Nexus Trace TG documentation and reference code☆51Updated 5 months ago
- This is the fork of CVA6 intended for PULP development.☆21Updated 3 weeks ago