ryanlorica / processing-engine
A Scala w/ Chisel based implementation of a processing engine generator for neural network accelerators.
☆10Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for processing-engine
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- ☆22Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- CNN accelerator☆26Updated 7 years ago
- Common SystemVerilog RTL modules for RgGen☆11Updated 6 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- ☆37Updated 5 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Algorithmic C Machine Learning Library☆22Updated 3 months ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆18Updated last month
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 7 years ago
- The Verilog source code for DRUM approximate multiplier.☆28Updated last year
- Craft 2 top-level repository☆13Updated 5 years ago
- HLS for Networks-on-Chip☆31Updated 3 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆17Updated 11 years ago
- Matrix Multiply and Accumulate unit written in System Verilog☆10Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year
- Reconfigurable Binary Engine☆15Updated 3 years ago
- Ratatoskr NoC Simulator☆21Updated 3 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆23Updated last month
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- eyeriss-chisel3☆39Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- SRAM☆20Updated 4 years ago