IObundle / iob-mem
Verilog behavioral description of various memories
☆30Updated 2 years ago
Alternatives and similar repositories for iob-mem:
Users that are interested in iob-mem are comparing it to the libraries listed below
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆42Updated 3 weeks ago
- ☆23Updated last month
- DUTH RISC-V Superscalar Microprocessor☆29Updated 3 months ago
- Wraps the NVDLA project for Chipyard integration☆19Updated 11 months ago
- Simple single-port AXI memory interface☆37Updated 8 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆62Updated this week
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 5 months ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆19Updated 9 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆34Updated 2 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 7 years ago
- The multi-core cluster of a PULP system.☆69Updated this week
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆18Updated 4 months ago
- Platform Level Interrupt Controller☆36Updated 9 months ago
- ☆40Updated 5 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆16Updated 9 months ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- ☆53Updated 4 years ago
- ☆41Updated last week
- PCI Express controller model☆48Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆59Updated 3 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆19Updated 3 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- Network on Chip for MPSoC☆26Updated last month
- Chisel Cheatsheet☆32Updated last year
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 8 months ago