roo16kie / MAC_VerilogLinks
Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .
☆12Updated 6 years ago
Alternatives and similar repositories for MAC_Verilog
Users that are interested in MAC_Verilog are comparing it to the libraries listed below
Sorting:
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆114Updated 5 years ago
- A verilog implementation for Network-on-Chip☆81Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆179Updated 6 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆144Updated 7 years ago
- ☆46Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆180Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆242Updated 2 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆41Updated 3 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆39Updated last year
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆131Updated 6 months ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆98Updated 6 years ago
- IC implementation of TPU☆146Updated 6 years ago
- ☆124Updated 5 years ago
- AXI总线连接器☆105Updated 5 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆13Updated last year
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- IC implementation of Systolic Array for TPU☆329Updated last year
- AXI DMA 32 / 64 bits☆124Updated 11 years ago
- 3×3脉动阵列乘法器☆50Updated 6 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆154Updated 8 months ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆65Updated 2 years ago
- IC Verification & SV Demo☆57Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆22Updated last year
- This is a verilog implementation of 4x4 systolic array multiplier☆76Updated 5 years ago