roo16kie / MAC_VerilogLinks
Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .
☆12Updated 6 years ago
Alternatives and similar repositories for MAC_Verilog
Users that are interested in MAC_Verilog are comparing it to the libraries listed below
Sorting:
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆160Updated 5 years ago
- ☆111Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆73Updated 3 months ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆33Updated 4 years ago
- An LeNet RTL implement onto FPGA☆48Updated 7 years ago
- ☆33Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆75Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆117Updated 3 weeks ago
- Convolutional accelerator kernel, target ASIC & FPGA☆205Updated 2 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆23Updated 7 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- ☆16Updated last year
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆14Updated 10 months ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- ☆65Updated 6 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆36Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆32Updated 2 years ago
- IC Verification & SV Demo☆54Updated 3 years ago
- ES-203 Computer Organization & Architecture CNN on FPGA board☆14Updated 3 years ago
- verilog实现systolic array及配套IO☆8Updated 6 months ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆60Updated last year
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆125Updated 7 years ago