Alternatives and similar repositories for VerilogCreator

Users that are interested in VerilogCreator are comparing it to the libraries listed below

• libresilicon / qtflow
  Free open source EDA tools
  ☆66Updated 6 years ago
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆115Updated 2 years ago
• ZipCPU / vgasim
  A Video display simulator
  ☆175Updated 8 months ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆125Updated 9 years ago
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆110Updated 5 months ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆186Updated last year
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆99Updated 3 years ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆131Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 10 months ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆72Updated 7 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆74Updated 4 years ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆65Updated 8 months ago
• rubund / graywolf
  ☆114Updated 4 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆34Updated 4 years ago
• Domipheus / TPU
  TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…
  ☆150Updated 9 years ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆80Updated 4 years ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆320Updated this week
• forflo / yodl
  A VHDL frontend for Yosys
  ☆104Updated 8 years ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆79Updated 3 years ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆142Updated 2 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆56Updated 7 years ago
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 4 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆82Updated 5 years ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆87Updated 2 years ago
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆202Updated 5 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆71Updated 3 years ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆189Updated last week
• m-labs / lm32
  LatticeMico32 soft processor
  ☆107Updated 11 years ago
• jhallen / vivado_setup
  How to set up Xilinx Vivado for source control
  ☆108Updated last year
• yne / vcd
  VCD file (Value Change Dump) command line viewer
  ☆120Updated 2 months ago