VerilogCreator is a QtCreator based IDE for Verilog 2005
☆171Aug 8, 2022Updated 3 years ago
Alternatives and similar repositories for VerilogCreator
Users that are interested in VerilogCreator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This is a stand-alone Verilog IDE derived from a QtCreator 3.6.1 subset featuring the VerilogCreator plugin☆20Aug 8, 2022Updated 3 years ago
- A basic documentation generator for Verilog, similar to Doxygen.☆13Aug 5, 2016Updated 9 years ago
- Programmable Arcade Circuit Emulation☆15Oct 14, 2017Updated 8 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Dec 20, 2019Updated 6 years ago
- This is the Verilog 2005 parser used by VerilogCreator☆15May 19, 2019Updated 7 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- A library and command-line tool for querying a Verilog netlist.☆30Jun 13, 2022Updated 4 years ago
- Experimental graphic editor for open FPGAs.☆50Mar 29, 2016Updated 10 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- ☆19Aug 30, 2020Updated 5 years ago
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- nMigen examples for the ULX3S board☆16Nov 30, 2020Updated 5 years ago
- Generate symbols from HDL components/modules☆22Feb 6, 2023Updated 3 years ago
- FlowLine2 is a modelling tool supporting Functional Analysis and Business Process Modelling☆16Aug 8, 2022Updated 3 years ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆65Sep 25, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Documenting the Lattice ECP5 bit-stream format.☆463May 9, 2026Updated 2 months ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- Example project for the BRS-100-GW1NR9 FPGA development board.☆19Jul 9, 2026Updated 3 weeks ago
- IRSIM switch-level simulator for digital circuits☆37Nov 13, 2025Updated 8 months ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- Icarus SIMBUS☆21Nov 6, 2019Updated 6 years ago
- A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.☆11Jan 21, 2018Updated 8 years ago
- Schematic symbol libraries for FPGAs & microcontrollers.☆113Sep 17, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This repository contain source code for ngspice and ghdl integration☆35Jun 3, 2026Updated last month
- FPGA Odysseus with ULX3S☆73Nov 1, 2023Updated 2 years ago
- FPGA code for NeTV2☆16Dec 3, 2018Updated 7 years ago
- ☆13Jun 21, 2026Updated last month
- wavedrom to verilog converter☆17Sep 14, 2021Updated 4 years ago
- Drawio => VHDL and Verilog☆62Oct 15, 2023Updated 2 years ago
- IO and periphery cells for SKY130 provided by SkyWater.☆14Nov 29, 2023Updated 2 years ago
- Builds, flow and designs for the alpha release☆55Dec 18, 2019Updated 6 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆21Nov 13, 2024Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ice40 UltraPlus demos☆16Oct 4, 2019Updated 6 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,206Feb 11, 2026Updated 5 months ago
- An abstraction library for interfacing EDA tools☆782Jul 2, 2026Updated 3 weeks ago
- ☆64Jul 21, 2020Updated 6 years ago
- Alliance VLSI CAD Tools (LIP6)☆23Dec 11, 2025Updated 7 months ago
- A utility for Composing FPGA designs from Peripherals☆192Jul 4, 2026Updated 3 weeks ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆35Jul 15, 2024Updated 2 years ago