jhallen / vivado_setupLinks
How to set up Xilinx Vivado for source control
☆106Updated 8 months ago
Alternatives and similar repositories for vivado_setup
Users that are interested in vivado_setup are comparing it to the libraries listed below
Sorting:
- FuseSoC standard core library☆139Updated last week
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆288Updated this week
- A simple RISC-V processor for use in FPGA designs.☆274Updated 9 months ago
- Example LED blinking project for your FPGA dev board of choice☆175Updated last week
- Example designs showing different ways to use F4PGA toolchains.☆276Updated last year
- A utility for Composing FPGA designs from Peripherals☆179Updated 5 months ago
- ☆79Updated last year
- A Video display simulator☆168Updated 2 weeks ago
- CoreScore☆155Updated 4 months ago
- Multi-platform nightly builds of open source FPGA tools☆296Updated 3 years ago
- An Open Source configuration of the Arty platform☆130Updated last year
- Experimental flows using nextpnr for Xilinx devices☆238Updated 7 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆116Updated 4 years ago
- Small footprint and configurable Ethernet core☆240Updated last week
- Bus bridges and other odds and ends☆563Updated last month
- HDL symbol generator☆189Updated 2 years ago
- VHDL library 4 FPGAs☆179Updated this week
- SystemVerilog synthesis tool☆194Updated 2 months ago
- A simple, basic, formally verified UART controller☆303Updated last year
- VHDL synthesis (based on ghdl)☆335Updated last week
- A 32-bit RISC-V soft processor☆311Updated 3 months ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 2 months ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆96Updated 3 years ago
- Verilog wishbone components☆115Updated last year
- A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.☆203Updated 3 years ago
- A wishbone controlled scope for FPGA's☆82Updated last year
- A single-wire bi-directional chip-to-chip interface for FPGAs☆121Updated 8 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 3 years ago
- Small footprint and configurable DRAM core☆415Updated last week
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆135Updated 3 years ago