Alternatives and similar repositories for vivado_setup

Users that are interested in vivado_setup are comparing it to the libraries listed below

• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 5 months ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆295Updated last week
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆185Updated 10 months ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆185Updated 2 weeks ago
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆299Updated 3 years ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆246Updated last year
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆265Updated 2 weeks ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆349Updated 3 weeks ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆316Updated 3 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆311Updated last year
• ZipCPU / vgasim
  A Video display simulator
  ☆174Updated 5 months ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated 2 weeks ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆163Updated last week
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆133Updated last year
• olofk / corescore
  CoreScore
  ☆166Updated last week
• pieter3d / simview
  ☆85Updated 2 weeks ago
• kevinpt / symbolator
  HDL symbol generator
  ☆195Updated 2 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆279Updated last year
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆403Updated last week
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆208Updated last year
• enjoy-digital / litescope
  Small footprint and configurable embedded FPGA logic analyzer
  ☆191Updated 2 weeks ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆84Updated last year
• ZipCPU / dblclockfft
  A configurable C++ generator of pipelined Verilog FFT cores
  ☆249Updated last year
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆123Updated 5 years ago
• yne / vcd
  VCD file (Value Change Dump) command line viewer
  ☆120Updated 2 years ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆201Updated last week
• SparcLab / OpenSERDES
  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
  ☆254Updated 3 years ago