Alternatives and similar repositories for vivado_setup

Users that are interested in vivado_setup are comparing it to the libraries listed below

• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆144Updated last month
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆179Updated 6 months ago
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆296Updated 3 years ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆240Updated 8 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆277Updated 10 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆305Updated last year
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆290Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆568Updated 2 months ago
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆247Updated last month
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆419Updated last month
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆390Updated this week
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆276Updated 5 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆198Updated 3 months ago
• pieter3d / simview
  ☆79Updated last year
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆129Updated last year
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆177Updated last month
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆417Updated last month
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆151Updated last week
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆166Updated 4 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆118Updated 4 years ago
• kevinpt / symbolator
  HDL symbol generator
  ☆190Updated 2 years ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆402Updated last month
• grahamedgecombe / icicle
  32-bit RISC-V system on chip for iCE40 FPGAs
  ☆308Updated 2 years ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆391Updated 5 months ago
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆435Updated 9 months ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆327Updated this week
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆335Updated last month
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆696Updated last week
• olofk / corescore
  CoreScore
  ☆156Updated 5 months ago