riscv / riscv-zfinx

Related projects: ⓘ

• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆25Updated last year
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated 10 months ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆17Updated 2 years ago
• ultraembedded / cortex_m0_wrapper
  Cortex-M0 DesignStart Wrapper
  ☆17Updated 5 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆14Updated last week
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated last year
• taneroksuz / fpu-sp
  IEEE 754 floating point library in system-verilog and vhdl
  ☆26Updated 4 months ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆32Updated 7 months ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆22Updated 2 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆24Updated 2 years ago
• joey1115 / Alpha64_R10000_Superscalar_Processor
  Alpha64 R10000 Two-Way Superscalar Processor
  ☆11Updated 5 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆19Updated this week
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆15Updated 2 months ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆53Updated this week
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 9 years ago
• 0ctobyte / procyon
  Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.
  ☆12Updated last year
• stnolting / neorv32-riscof
  ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆25Updated this week
• phthinh / soric_project
  Source-Opened RISCV for Crypto
  ☆13Updated 2 years ago
• PacoReinaCampo / PU-RISCV
  Processing Unit with RISCV-32 / RISCV-64 / RISCV-128
  ☆19Updated this week
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆29Updated 3 years ago
• furkanturan / lowrisc-zed
  LowRISC port to Zedboard
  ☆12Updated 7 years ago
• The-OpenROAD-Project / OpenROAD-Cloud
  The source code that empowers OpenROAD Cloud
  ☆11Updated 4 years ago
• riscveval / Rocket-Chip
  ☆21Updated 7 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆29Updated 2 years ago
• freecores / sc2v
  SystemC to Verilog Synthesizable Subset Translator
  ☆9Updated last year
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆28Updated 8 years ago
• rdolbeau / VexRiscvBPluginGenerator
  ☆17Updated 2 years ago
• bwitherspoon / rv32cpu
  A RISC-V processor
  ☆13Updated 5 years ago
• CTSRD-CHERI / garnet
  Amazon F1-inspired Xilinx VCU118 hardware design framework
  ☆10Updated 3 years ago
• iammituraj / FIFOs
  Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
  ☆14Updated last month