Alternatives and similar repositories for Alpha64_R10000_Superscalar_Processor

Users that are interested in Alpha64_R10000_Superscalar_Processor are comparing it to the libraries listed below

• GabbedT / ApogeoRV
  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
  ☆17Updated 4 months ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆17Updated 6 years ago
• ehw-fit / approx-fpgas
  Approximate arithmetic circuits for FPGAs
  ☆12Updated 5 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 9 months ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆19Updated 2 months ago
• pulp-platform / rbe
  Reconfigurable Binary Engine
  ☆17Updated 4 years ago
• pulp-platform / axi_llc
  ☆30Updated 2 weeks ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆32Updated 2 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 5 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆20Updated 11 months ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 3 years ago
• robgiorgi / freess
  RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm
  ☆24Updated last month
• PeterMonsson / sv_waveterm
  ☆10Updated last year
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆26Updated last month
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆38Updated last month
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆17Updated 6 years ago
• CMU-SAFARI / MIG-7-PHY-DDR3-Controller
  A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.
  ☆11Updated 3 years ago
• sld-columbia / esp-caches
  SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
  ☆17Updated 5 months ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆19Updated 2 months ago
• coleblackman / TIDENet
  TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…
  ☆17Updated 2 years ago
• pulp-platform / jtag_pulp
  ☆13Updated 2 years ago
• antmicro / astsee
  ☆13Updated last month
• jieltan / OpenCompArchCourse
  ☆22Updated 4 years ago
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆23Updated 3 months ago
• IBM / esp-chisel-accelerators
  Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
  ☆24Updated 5 years ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆22Updated last year
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆31Updated 8 years ago