Alternatives and similar repositories for Alpha64_R10000_Superscalar_Processor

Users that are interested in Alpha64_R10000_Superscalar_Processor are comparing it to the libraries listed below

• ucb-bar / nvdla-wrapper
  Wraps the NVDLA project for Chipyard integration
  ☆20Updated last month
• pulp-platform / rbe
  Reconfigurable Binary Engine
  ☆16Updated 4 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 7 months ago
• GeekAlexis / superscalar-mips
  A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines
  ☆11Updated 5 years ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆23Updated 2 weeks ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆16Updated 5 years ago
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆27Updated 5 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆23Updated last week
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆19Updated 11 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• armleo / ArmleoCPU
  ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set
  ☆6Updated 2 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆16Updated 5 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆32Updated last year
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆25Updated this week
• ehw-fit / approx-fpgas
  Approximate arithmetic circuits for FPGAs
  ☆12Updated 5 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• ic-lab-duth / Fast-Float4HLS
  Fast Floating Point Operators for High Level Synthesis
  ☆21Updated 2 years ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆19Updated 2 weeks ago
• ucb-bar / esp-isa-sim
  Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
  ☆17Updated 2 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆37Updated 3 weeks ago
• GabbedT / ApogeoRV
  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
  ☆17Updated last month
• 0ctobyte / procyon
  Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.
  ☆12Updated 2 years ago
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆26Updated last year
• IBM / esp-chisel-accelerators
  Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
  ☆24Updated 5 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 5 months ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 3 years ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆21Updated 3 years ago
• m-asiatici / MSHR-rich
  A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…
  ☆20Updated 4 years ago