joey1115 / Alpha64_R10000_Superscalar_Processor
Alpha64 R10000 Two-Way Superscalar Processor
☆11Updated 5 years ago
Alternatives and similar repositories for Alpha64_R10000_Superscalar_Processor:
Users that are interested in Alpha64_R10000_Superscalar_Processor are comparing it to the libraries listed below
- Reconfigurable Binary Engine☆15Updated 3 years ago
- RISC-V soft-core PEs for TaPaSCo☆17Updated 7 months ago
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆29Updated 2 months ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- ☆21Updated last week
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Updated last year
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆16Updated 2 weeks ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆14Updated this week
- Approximate arithmetic circuits for FPGAs☆11Updated 4 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆19Updated 2 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆25Updated this week
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆31Updated 4 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆32Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆30Updated last year
- APB Logic☆12Updated last month
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Updated 5 years ago
- ☆21Updated this week
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆14Updated 4 months ago
- Neural Network accelerator powered by MVUs and RISC-V.☆12Updated 5 months ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 4 years ago
- ☆9Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 3 months ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- ☆12Updated 6 months ago
- ☆33Updated 2 years ago
- Verilog behavioral description of various memories☆30Updated 2 years ago
- ☆11Updated 10 months ago