furkanturan / lowrisc-zed
LowRISC port to Zedboard
☆12Updated 7 years ago
Related projects ⓘ
Alternatives and complementary repositories for lowrisc-zed
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Extensible FPGA control platform☆53Updated last year
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated 10 months ago
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- Wishbone interconnect utilities☆36Updated 5 months ago
- Hamming ECC Encoder and Decoder to protect memories☆28Updated last month
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆14Updated 2 months ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆26Updated 3 weeks ago
- ☆57Updated 3 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆41Updated 3 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 7 years ago
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 4 years ago
- Platform Level Interrupt Controller☆35Updated 6 months ago
- ☆46Updated 3 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆30Updated last year
- Cortex-M0 DesignStart Wrapper☆17Updated 5 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆20Updated 6 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 3 months ago
- ☆24Updated 4 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- Verilog Ethernet components for FPGA implementation☆14Updated last year
- JTAG DPI module for SystemVerilog RTL simulations☆25Updated 9 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆20Updated last week
- ☆25Updated 4 years ago