Alternatives and similar repositories for lowrisc-zed:

Users that are interested in lowrisc-zed are comparing it to the libraries listed below

• alexforencich / xfcp
  Extensible FPGA control platform
  ☆55Updated last year
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 6 months ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆29Updated 3 months ago
• pliu6 / vhd2vl
  vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.
  ☆26Updated 9 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆19Updated 10 years ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆32Updated 10 years ago
• ultraembedded / cortex_m0_wrapper
  Cortex-M0 DesignStart Wrapper
  ☆17Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated 7 months ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆32Updated 4 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 8 months ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆33Updated 6 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• RoaLogic / ahb3lite_memory
  Multi-Technology RAM with AHB3Lite interface
  ☆21Updated 8 months ago
• aignacio / mpsoc_example
  ☆58Updated 3 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆30Updated last year
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆55Updated 4 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆62Updated 4 years ago
• iammituraj / FIFOs
  Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
  ☆15Updated 5 months ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆31Updated 10 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆20Updated 3 weeks ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 6 years ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆19Updated 2 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• corundum / verilog-pcie
  Verilog PCI express components
  ☆20Updated last year