iammituraj / FIFOs
Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
☆14Updated 3 months ago
Related projects ⓘ
Alternatives and complementary repositories for FIFOs
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆18Updated 6 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆20Updated 3 weeks ago
- DDR4 Simulation Project in System Verilog☆32Updated 10 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆26Updated 9 years ago
- Verilog Ethernet components for FPGA implementation☆14Updated last year
- Hamming ECC Encoder and Decoder to protect memories☆28Updated last month
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆39Updated 7 years ago
- ☆13Updated last year
- Verilog Code for a JPEG Decoder☆31Updated 6 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆26Updated 3 years ago
- Extensible FPGA control platform☆54Updated last year
- ☆12Updated 3 years ago
- SystemVerilog Logger☆16Updated 2 years ago
- APB Logic☆12Updated 9 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- HDMI + GPU-pipeline + FFT☆13Updated 8 years ago
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆19Updated 6 years ago
- IP Cores that can be used within Vivado☆24Updated 3 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 3 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆19Updated 3 weeks ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆15Updated 4 months ago
- ☆13Updated 3 years ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆4Updated 2 years ago
- LowRISC port to Zedboard☆12Updated 7 years ago