iammituraj / FIFOs
Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
☆17Updated 8 months ago
Alternatives and similar repositories for FIFOs:
Users that are interested in FIFOs are comparing it to the libraries listed below
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 3 months ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 3 months ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆18Updated 7 years ago
- Ethernet MAC 10/100 Mbps☆26Updated 3 years ago
- USB -> AXI Debug Bridge☆36Updated 3 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated this week
- Network on Chip for MPSoC☆26Updated last week
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 3 years ago
- HDMI + GPU-pipeline + FFT☆13Updated 9 years ago
- ☆16Updated 6 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Advanced Debug Interface☆14Updated 3 months ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- An Ethernet MAC conforming to IEEE 802.3☆21Updated 7 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆13Updated 7 months ago
- ☆20Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- AXI X-Bar☆19Updated 5 years ago
- ☆13Updated last month
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago