iammituraj / FIFOs
Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
☆15Updated 5 months ago
Alternatives and similar repositories for FIFOs:
Users that are interested in FIFOs are comparing it to the libraries listed below
- This is the repository for a verilog implementation of a lzrw1 compression core☆18Updated 7 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 4 years ago
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- DDR4 Simulation Project in System Verilog☆32Updated 10 years ago
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆21Updated last month
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- Hamming ECC Encoder and Decoder to protect memories☆29Updated 3 months ago
- Generic AXI master stub☆19Updated 10 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Groundhog - Serial ATA Host Bus Adapter☆21Updated 6 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Software☆19Updated 2 years ago
- Xilinx IP repository☆13Updated 6 years ago
- ☆16Updated 5 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆12Updated 5 years ago
- Network on Chip for MPSoC☆25Updated 3 weeks ago
- MIPI CSI-2 RX☆30Updated 3 years ago
- ☆21Updated last week
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆20Updated 3 weeks ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆27Updated 3 years ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆31Updated 5 years ago
- Implementation of the PCIe physical layer☆32Updated this week
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 7 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆30Updated 3 weeks ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- SoC Based on ARM Cortex-M3☆25Updated this week