riscv / configuration-structure
RISC-V Configuration Structure
☆38Updated 6 months ago
Alternatives and similar repositories for configuration-structure:
Users that are interested in configuration-structure are comparing it to the libraries listed below
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆145Updated 6 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- ☆86Updated 2 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆31Updated last year
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Updated 4 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- ☆42Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- UNSUPPORTED INTERNAL toolchain builds☆38Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- ☆25Updated 2 months ago
- GDB server to debug CPU simulation waveform traces☆44Updated 3 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆33Updated this week
- Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...☆52Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆96Updated last month
- The multi-core cluster of a PULP system.☆90Updated last week
- ☆29Updated 2 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- OmniXtend cache coherence protocol☆82Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- The RISC-V External Debug Security Specification☆19Updated last week
- ☆29Updated 2 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- RISC-V Nexus Trace TG documentation and reference code☆50Updated 4 months ago
- Simple runtime for Pulp platforms☆45Updated last month
- Naive Educational RISC V processor☆82Updated 6 months ago
- HW Design Collateral for Caliptra RoT IP☆90Updated last week
- ☆84Updated last week
- An open-source custom cache generator.☆33Updated last year
- Small footprint and configurable Inter-Chip communication cores☆57Updated 2 weeks ago