tenstorrent / rv-core-dv-kit
☆25Updated 2 months ago
Alternatives and similar repositories for rv-core-dv-kit:
Users that are interested in rv-core-dv-kit are comparing it to the libraries listed below
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆16Updated 2 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆36Updated 3 years ago
- SCARV: a side-channel hardened RISC-V platform☆26Updated 2 years ago
- An open-source custom cache generator.☆33Updated last year
- Demo SoC for SiliconCompiler.☆59Updated 2 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- ☆55Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆96Updated last month
- ☆46Updated this week
- Platform Level Interrupt Controller☆40Updated 11 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆62Updated 11 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆31Updated last year
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆33Updated this week
- ☆42Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- ☆92Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆41Updated 2 years ago
- Simple runtime for Pulp platforms☆45Updated last month
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆91Updated last month
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- ☆33Updated 2 years ago
- The multi-core cluster of a PULP system.☆90Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 8 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 9 months ago