tenstorrent / rv-core-dv-kitLinks
☆25Updated 6 months ago
Alternatives and similar repositories for rv-core-dv-kit
Users that are interested in rv-core-dv-kit are comparing it to the libraries listed below
Sorting:
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- ☆50Updated 4 months ago
- The multi-core cluster of a PULP system.☆108Updated this week
- ☆27Updated 6 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆43Updated 2 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 6 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆119Updated 2 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 4 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- RISC-V Nexus Trace TG documentation and reference code☆52Updated 8 months ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- ☆33Updated 2 years ago
- OmniXtend cache coherence protocol☆82Updated 3 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 10 months ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆65Updated 10 months ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- SoftCPU/SoC engine-V☆54Updated 5 months ago
- ☆90Updated 2 weeks ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated 3 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year