riscv-software-src / riscv-unified-db

Related projects ⓘ

Alternatives and complementary repositories for riscv-unified-db

• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆80Updated 2 weeks ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆57Updated this week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆96Updated this week
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆27Updated 6 months ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆33Updated this week
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆15Updated 2 weeks ago
• riscv / riscv-CMOs
  ☆81Updated 2 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆63Updated last month
• riscv / virtual-memory
  ☆35Updated 3 years ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆44Updated this week
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆112Updated last month
• chipsalliance / espresso
  ☆36Updated 9 months ago
• riscv / riscv-aclint
  ☆39Updated 2 years ago
• riscv / riscv-bfloat16
  ☆30Updated 4 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated 7 months ago
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆43Updated this week
• sifive / chisel-circt
  Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
  ☆70Updated last year
• stnolting / neorv32-riscof
  ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆25Updated this week
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆46Updated this week
• riscv-non-isa / riscv-semihosting
  ☆28Updated 2 weeks ago
• tenstorrent / rv-core-dv-kit
  ☆24Updated 2 years ago
• sifive / block-inclusivecache-sifive
  ☆75Updated 2 years ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆14Updated 7 months ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆35Updated 11 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆58Updated 2 months ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆76Updated this week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆56Updated 2 weeks ago
• riscv-software-src / riscof
  ☆66Updated last month
• riscvarchive / riscv-code-size-reduction
  ☆150Updated 8 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆60Updated this week