Alternatives and similar repositories for riscv-unified-db

Users that are interested in riscv-unified-db are comparing it to the libraries listed below

• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆126Updated last week
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆74Updated last week
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆143Updated this week
• riscv-software-src / riscof
  ☆85Updated 4 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆191Updated last week
• riscvarchive / riscv-code-size-reduction
  ☆149Updated last year
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆167Updated 2 weeks ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆160Updated 6 months ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆81Updated last month
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆190Updated 3 months ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆151Updated 2 months ago
• riscv / riscv-CMOs
  ☆89Updated 3 years ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆147Updated 9 months ago
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆111Updated 3 weeks ago
• riscv-non-isa / iopmp-spec
  This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…
  ☆30Updated 2 weeks ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆85Updated 3 weeks ago
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆111Updated 2 months ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆272Updated 2 weeks ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆113Updated last week
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆152Updated this week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 8 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆89Updated this week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆241Updated 9 months ago
• riscv / riscv-cfi
  This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …
  ☆91Updated 2 weeks ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆144Updated last week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• SpinalHDL / NaxRiscv
  ☆293Updated last month
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆44Updated last month
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆196Updated last year
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆101Updated last week