Alternatives and similar repositories for riscv-cheri

Users that are interested in riscv-cheri are comparing it to the libraries listed below

• riscv-software-src / riscv-unified-db
  Monorepo containing a machine-readable database of the RISC-V specification and artifact generation tools
  ☆106Updated this week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆130Updated last week
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆113Updated last month
• riscv-software-src / riscof
  ☆92Updated last month
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆166Updated 3 weeks ago
• riscvarchive / riscv-CMOs
  ☆90Updated last month
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆64Updated 2 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆150Updated this week
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆41Updated 11 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 11 months ago
• riscv / riscv-cfi
  This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …
  ☆92Updated 2 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 10 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆194Updated last month
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆60Updated last week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 4 months ago
• lowRISC / sonata-system
  A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
  ☆45Updated this week
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆46Updated last month
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆147Updated last month
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 2 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆197Updated last year
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆112Updated this week
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆215Updated last year
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆227Updated last year
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆112Updated 2 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆219Updated 4 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆162Updated 5 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆245Updated 10 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆158Updated 3 years ago
• riscv / riscv-aia
  ☆96Updated last month