pwwpche / CSE240-Branch-PredictorView external linksLinks
Course project of UCSD CSE-240A Computer Architecture
☆18Jul 8, 2017Updated 8 years ago
Alternatives and similar repositories for CSE240-Branch-Predictor
Users that are interested in CSE240-Branch-Predictor are comparing it to the libraries listed below
Sorting:
- UCSD CSE240A Project: Branch Predictor☆11Jul 24, 2017Updated 8 years ago
- ☆11Jul 2, 2024Updated last year
- Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud☆20May 7, 2018Updated 7 years ago
- Development of a Network on Chip Simulation using SystemC.☆34Jul 14, 2017Updated 8 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆48Updated this week
- Luthier, a GPU binary instrumentation tool for AMD GPUs☆26Updated this week
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- ☆13Jan 28, 2026Updated 2 weeks ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- ☆20Sep 11, 2025Updated 5 months ago
- This repository contains software for BeagleWire. Docs of BeagleWire: https://beaglewire.github.io/☆11Aug 17, 2021Updated 4 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- (SIGIR 25) Repo for "Review-driven Personalized Preference Reasoning with Large Language Models for Recommendation"☆10Jan 18, 2025Updated last year
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆46Jan 2, 2025Updated last year
- VHDL Implementation☆13Oct 9, 2014Updated 11 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆11Feb 22, 2018Updated 7 years ago
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Jun 5, 2017Updated 8 years ago
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Aug 30, 2016Updated 9 years ago
- ☆12Aug 8, 2024Updated last year
- Top level for the November shuttle☆12Nov 20, 2021Updated 4 years ago
- Not All Patches Are Equal: Hierarchical Dataset Condensation for Single Image Super-Resolution☆10May 7, 2024Updated last year
- ☆14Oct 30, 2024Updated last year
- [PACT'24] GraNNDis. A fast and unified distributed graph neural network (GNN) training framework for both full-batch (full-graph) and min…☆10Aug 13, 2024Updated last year
- UART cocotb module☆11Jun 30, 2021Updated 4 years ago
- Fork of the gem5 simulator with Garnet2.0 and DSENT extensions☆13Jan 28, 2019Updated 7 years ago
- An official code of Densely-packed Object Detection via Hard Negative-Aware Anchor Attention in WACV2022☆12Jan 6, 2022Updated 4 years ago
- Wishbone bridge over SPI☆11Nov 13, 2019Updated 6 years ago
- ☆41Feb 28, 2022Updated 3 years ago
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆13Aug 23, 2024Updated last year
- (elastic) cuckoo hashing☆15Jun 20, 2020Updated 5 years ago
- ☆19Jan 28, 2025Updated last year
- USB-to-PS2 mouse controller for FPGAs written in Verilog. Performs clock division, signal sampling, processing, error checking, and valid…☆17Feb 26, 2022Updated 3 years ago
- ☆13Oct 6, 2024Updated last year
- Matrix multiplication accelerator on ZYNQ SoC.☆12Apr 29, 2025Updated 9 months ago
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆12Jan 24, 2022Updated 4 years ago
- Automatically exported from code.google.com/p/tpzsimul☆12Jul 7, 2015Updated 10 years ago
- All you need to build and run SystemC and AccessNoxim on your system; SystemC and AccessNoxim are tools to emulate and test network-on-ch…☆14Dec 17, 2017Updated 8 years ago
- ☆17Oct 15, 2023Updated 2 years ago
- ☆14Feb 24, 2025Updated 11 months ago