Course project of UCSD CSE-240A Computer Architecture
☆20Jul 8, 2017Updated 9 years ago
Alternatives and similar repositories for CSE240-Branch-Predictor
Users that are interested in CSE240-Branch-Predictor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- UCSD CSE240A Project: Branch Predictor☆11Jul 24, 2017Updated 9 years ago
- Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud☆22May 7, 2018Updated 8 years ago
- ☆12Jul 2, 2024Updated 2 years ago
- ☆19Nov 6, 2024Updated last year
- An official code of Densely-packed Object Detection via Hard Negative-Aware Anchor Attention in WACV2022☆12Jan 6, 2022Updated 4 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆25Nov 21, 2020Updated 5 years ago
- A branch predictor simulator in C++ that tests 6 different types of branch predictors.☆13Apr 26, 2018Updated 8 years ago
- ☆14Nov 27, 2021Updated 4 years ago
- ☆13Sep 9, 2026Updated last week
- Ready-to-link, packaged Aurora IP on four QSFP28 lanes, providing 100Gb/s throughput, flow control and status monitoring☆19Sep 7, 2026Updated last week
- Wishbone bridge over SPI☆11Nov 13, 2019Updated 6 years ago
- Top level for the November shuttle☆13Nov 20, 2021Updated 4 years ago
- This repository contains a number of ROS/ROS2 nodes for various robotics applications that can operate in real-time on the Qualcomm Robot…☆16Oct 7, 2023Updated 2 years ago
- BTB-X HPCA23 code☆13Jan 6, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- [ICCAD'22 TinyML Contest] Efficient Heart Stroke Detection on Low-cost Microcontrollers☆15Jan 12, 2023Updated 3 years ago
- Verilog implementation of 16-bit multi-cycle RISC15 processor design☆16Nov 4, 2015Updated 10 years ago
- Multimedia SoC Design with Specialization on Application Acceleration with High-Level-Synthesis [2020 Fall]☆12Jun 15, 2021Updated 5 years ago
- This repository contains software for BeagleWire. Docs of BeagleWire: https://beaglewire.github.io/☆12Aug 17, 2021Updated 5 years ago
- MAC system with IEEE754 compatibility☆14Nov 22, 2023Updated 2 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆13Feb 22, 2018Updated 8 years ago
- DaCH: dataflow cache for high-level synthesis.☆20Jul 27, 2023Updated 3 years ago
- BadgerTrap is a tool to instrument x86-64 TLB misses.☆13Nov 13, 2016Updated 9 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Web-based RISC-V superscalar simulator☆21Mar 23, 2025Updated last year
- ☆10Nov 19, 2015Updated 10 years ago
- An example model of a Network Processing Unit using the PFPSim framework.☆13Aug 23, 2016Updated 10 years ago
- ☆13Apr 15, 2025Updated last year
- It is a fpga implementation of an i2c master, framebuffer for sdd1306 display☆12May 14, 2021Updated 5 years ago
- A simple cache simulator☆21Jan 14, 2019Updated 7 years ago
- (elastic) cuckoo hashing☆17Jun 20, 2020Updated 6 years ago
- Utility for accessing standard Linux spidev devices from userspace.☆11Jan 18, 2017Updated 9 years ago
- ☆14Oct 30, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆15Nov 12, 2023Updated 2 years ago
- HLS implemented systolic array structure☆41Nov 13, 2017Updated 8 years ago
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Jun 5, 2017Updated 9 years ago
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Aug 30, 2016Updated 10 years ago
- Misc iCE40 specific cores☆14Feb 13, 2023Updated 3 years ago
- [PACT'24] GraNNDis. A fast and unified distributed graph neural network (GNN) training framework for both full-batch (full-graph) and min…☆10Aug 13, 2024Updated 2 years ago
- Collection of PhD Advice Links☆23Oct 14, 2022Updated 3 years ago