kachris / survey_HA_LLM
A survey on Hardware Accelerated LLMs
☆50Updated 2 months ago
Alternatives and similar repositories for survey_HA_LLM:
Users that are interested in survey_HA_LLM are comparing it to the libraries listed below
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆49Updated 2 weeks ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆89Updated 6 months ago
- Machine-Learning Accelerator System Exploration Tools☆153Updated this week
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆77Updated 8 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆132Updated this week
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆48Updated last week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated last month
- ☆53Updated 2 weeks ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆99Updated last month
- ☆33Updated this week
- ☆48Updated last week
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆75Updated last month
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆141Updated last month
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆165Updated this week
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆31Updated this week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆121Updated last week
- A DSL for Systolic Arrays☆79Updated 6 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆70Updated 5 years ago
- ☆87Updated 9 months ago
- RTL implementation of Flex-DPE.☆98Updated 5 years ago
- An FPGA Accelerator for Transformer Inference☆78Updated 2 years ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆50Updated last year
- ☆28Updated 3 years ago
- ☆71Updated 2 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆45Updated this week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆70Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆51Updated 3 weeks ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆58Updated 5 months ago
- An Open-Source Tool for CGRA Accelerators☆60Updated 2 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆62Updated 9 months ago