kachris / survey_HA_LLM
A survey on Hardware Accelerated LLMs
☆49Updated 2 months ago
Alternatives and similar repositories for survey_HA_LLM:
Users that are interested in survey_HA_LLM are comparing it to the libraries listed below
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆48Updated this week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated 3 weeks ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆77Updated 7 months ago
- Machine-Learning Accelerator System Exploration Tools☆149Updated this week
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆86Updated 5 months ago
- ☆52Updated this week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆130Updated 2 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆46Updated 5 months ago
- ☆33Updated last week
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆68Updated 5 years ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆135Updated 2 weeks ago
- ☆38Updated 3 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆36Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆29Updated 7 months ago
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆123Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆69Updated 3 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆37Updated 2 years ago
- ☆23Updated 7 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆94Updated last month
- RTL implementation of Flex-DPE.☆98Updated 5 years ago
- ☆57Updated last year
- A DSL for Systolic Arrays☆79Updated 6 years ago
- ☆47Updated 3 weeks ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆31Updated last week
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆48Updated last week
- A fast, accurate trace-based simulator for High-Level Synthesis.☆45Updated last month
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆55Updated 3 years ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆49Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 weeks ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆36Updated last month