Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.
☆34May 1, 2021Updated 5 years ago
Alternatives and similar repositories for Computer-Architecture
Users that are interested in Computer-Architecture are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆12Feb 16, 2019Updated 7 years ago
- An example Hardware Processing Engine☆12Feb 4, 2023Updated 3 years ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Aug 9, 2026Updated last month
- Parallel Array of Simple Cores. Multicore processor.☆101May 16, 2019Updated 7 years ago
- Polyexen demo of Plonkish Arithmetiation Format (Plaf) on the zkevm-circuits☆31Feb 16, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Aug 9, 2026Updated last month
- ☆41Jan 7, 2024Updated 2 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆28Jul 27, 2026Updated last month
- Verify a chain of x509 certificates in halo2☆33Nov 30, 2023Updated 2 years ago
- VexRiscv-SMP integration test with LiteX.☆26Nov 16, 2020Updated 5 years ago
- a simple riscv cpu☆24Dec 2, 2022Updated 3 years ago
- Network on Chip for MPSoC☆30Aug 7, 2026Updated last month
- PyTorch code for full quantization of DNN using BCGD☆14Jul 24, 2019Updated 7 years ago
- Video Effects on VGA☆15Jan 7, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A program for creating and verifying zkSNARKs to prove the results of Orbis smart contract executions and other TinyRAM program execution…☆39Nov 18, 2022Updated 3 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆27Aug 23, 2021Updated 5 years ago
- ☆10Apr 18, 2023Updated 3 years ago
- A vector graphics renderer for bgfx, based on ideas from NanoVG and ImDrawList (Dear ImGUI)☆11Sep 14, 2026Updated last week
- [wip] implementing origami VDF☆13Mar 1, 2023Updated 3 years ago
- ☆14May 15, 2023Updated 3 years ago
- C Compiler written in Kotlin☆13Apr 19, 2024Updated 2 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆41Feb 6, 2024Updated 2 years ago
- Open-Source Libraries for Circom by ABDK Consulting☆18Dec 22, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Aug 9, 2026Updated last month
- MESMERIC: A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies☆10Oct 1, 2020Updated 5 years ago
- Demo of simulating kicad schematics in spice☆12Apr 30, 2015Updated 11 years ago
- https://hackaday.io/project/172073-microcoding-for-fpgas☆16Nov 11, 2025Updated 10 months ago
- A C11 compiler for the discrete logic computer☆21Apr 3, 2024Updated 2 years ago
- ☆13Feb 8, 2021Updated 5 years ago
- ☆17Jan 22, 2023Updated 3 years ago
- The Milkymist GUI toolkit (Genode FX based), because X11 sucks!☆14Jul 12, 2011Updated 15 years ago
- A python REPL and Editor and console based on Qt.☆14Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- C++ simple OS (mostly a kernel at the moment)☆12Mar 12, 2017Updated 9 years ago
- Development area for another repo: Learn_Bluespec_and_RISCV_Design☆13Jun 28, 2026Updated 2 months ago
- Wiki lives in here☆12Jun 11, 2020Updated 6 years ago
- SPIR-V fragment shader GPU core based on RISC-V☆47May 26, 2021Updated 5 years ago
- Direct Access Memory for MPSoC☆13Aug 7, 2026Updated last month
- Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations☆14Jan 22, 2020Updated 6 years ago
- ☆10Dec 28, 2020Updated 5 years ago