princeofpython / Computer-ArchitectureLinks
Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.
☆28Updated 4 years ago
Alternatives and similar repositories for Computer-Architecture
Users that are interested in Computer-Architecture are comparing it to the libraries listed below
Sorting:
- A Hardware Implemented Poseidon Hasher☆18Updated 3 years ago
- RV32I Single Cycle Processor (CPU)☆11Updated 3 years ago
- Simple 8-bit UART realization on Verilog HDL.☆107Updated last year
- Various caches written in Verilog-HDL☆125Updated 10 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- Vector processor for RISC-V vector ISA☆121Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆62Updated 5 months ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆59Updated 11 months ago
- Verilog/SystemVerilog Guide☆68Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆99Updated last year
- ☆81Updated last year
- Complete tutorial code.☆21Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last week
- Elgamal's over Elliptic Curves☆19Updated 6 years ago
- An Open-Source Design and Verification Environment for RISC-V☆83Updated 4 years ago
- IEEE 754 floating point unit in Verilog☆142Updated 9 years ago
- ePIC (Embedded PIC) example: kernel and relocatable loadable app☆14Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆102Updated 2 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆111Updated last week
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆101Updated last month
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆78Updated last week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated this week
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆54Updated last week
- Simple cache design implementation in verilog☆49Updated last year
- RISC-V Functional ISA Simulator☆17Updated 3 weeks ago
- 6-stage in-order dual-issue superscalar risc-v cpu with floating point unit☆13Updated this week
- A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall☆50Updated 5 months ago
- my UVM training projects☆34Updated 6 years ago
- RISC-V Verification Interface☆97Updated last month
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated 11 months ago