hedgeberg / VerilogCommonLinks
A repo of basic Verilog/SystemVerilog modules useful in other circuits.
☆21Updated 7 years ago
Alternatives and similar repositories for VerilogCommon
Users that are interested in VerilogCommon are comparing it to the libraries listed below
Sorting:
- 妖刀夢渡☆59Updated 6 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- Industry standard I/O for Amaranth HDL☆28Updated 7 months ago
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- Miscellaneous ULX3S examples (advanced)☆77Updated 2 weeks ago
- Project X-Ray Database: XC7 Series☆69Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- SDRAM controller with multiple wishbone slave ports☆29Updated 6 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- ☆22Updated 3 years ago
- DVI video out example for prjtrellis☆16Updated 6 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 10 months ago
- Board and connector definition files for nMigen☆30Updated 4 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated last week
- Tools for FPGA development.☆45Updated 2 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Updated 7 years ago
- PicoRV☆44Updated 5 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- ☆60Updated last year
- Altera JTAG UART wrapper for Bluespec☆25Updated 11 years ago
- iCE40 floorplan viewer☆24Updated 6 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- understanding the tinyfpga bootloader☆24Updated 7 years ago
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆37Updated 2 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- FPGA USB 1.1 Low-Speed Implementation☆34Updated 6 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆91Updated 5 years ago
- A wishbone controlled scope for FPGA's☆82Updated last year