hedgeberg / VerilogCommon

Related projects ⓘ

Alternatives and complementary repositories for VerilogCommon

• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆36Updated last year
• softminus / HEAI
  fun with GSM
  ☆2Updated 3 years ago
• whitequark / Yumewatari
  妖刀夢渡
  ☆56Updated 5 years ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆26Updated last month
• daveshah1 / prjtrellis-dvi
  DVI video out example for prjtrellis
  ☆16Updated 5 years ago
• mattvenn / understanding-tinyfpga-bootloader
  understanding the tinyfpga bootloader
  ☆24Updated 6 years ago
• barawn / xvcd-anita
  XVCD implementation for ANITA. Note that "ftdi_xvc_core.c" is a generic libftdi-based MPSSE XVC handler, and is awesome.
  ☆18Updated 4 years ago
• thotypous / alterajtaguart
  Altera JTAG UART wrapper for Bluespec
  ☆24Updated 10 years ago
• YosysHQ / prjtrellis-db
  Project Trellis database
  ☆12Updated last year
• skristiansson / wb_sdram_ctrl
  SDRAM controller with multiple wishbone slave ports
  ☆28Updated 6 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆40Updated 7 months ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆36Updated 3 years ago
• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 6 years ago
• knielsen / ice40_viewer
  ☆58Updated last year
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆20Updated last year
• emard / ulx3s-misc
  Miscellaneous ULX3S examples (advanced)
  ☆74Updated last year
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆30Updated 4 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• ZipCPU / wbfmtx
  A wishbone controlled FM transmitter hack
  ☆21Updated 10 months ago
• semify-eda / waveform-generator
  Waveform Generator
  ☆11Updated 2 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• tomverbeure / intel_jtag_primitive_blog
  How to use the Intel JTAG primitive without using virtual JTAG
  ☆16Updated 3 years ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆73Updated 10 months ago
• lawrie / tiny_usb_examples
  Using the TinyFPGA BX USB code in user designs
  ☆49Updated 5 years ago
• no2fpga / no2muacm
  Drop In USB CDC ACM core for iCE40 FPGA
  ☆33Updated 3 years ago
• sparrowgrine / prjtritium
  ☆22Updated 2 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆44Updated last week
• brouhaha / xchange
  Change part number or package in a Xilinx 7-series FPGA bitstream
  ☆36Updated 4 years ago