Alternatives and similar repositories for RISC-Verdi

Users that are interested in RISC-Verdi are comparing it to the libraries listed below

• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated 10 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆61Updated last year
• pulp-platform / axi_llc
  ☆30Updated 2 weeks ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆49Updated 3 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated last year
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆50Updated 10 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆43Updated last year
• PacoReinaCampo / vhdl2verilog
  Hardware Description Language Translator
  ☆17Updated 5 months ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆68Updated 3 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆31Updated 5 months ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated 2 weeks ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆70Updated this week
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆48Updated last week
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆66Updated last year
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆30Updated 7 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆20Updated 5 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆111Updated last week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated 3 weeks ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆46Updated last year
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆25Updated 2 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆67Updated 8 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 4 years ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆59Updated this week
• chipsalliance / uvm-verilator
  ☆103Updated this week
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago