Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
☆33Feb 6, 2020Updated 6 years ago
Alternatives and similar repositories for RISC-Verdi
Users that are interested in RISC-Verdi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol☆13Jul 11, 2018Updated 7 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last month
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 6 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated 10 months ago
- Used for hardware trojan detection（Based on Trust_Hub）☆10Jul 30, 2019Updated 6 years ago
- A stream to RTL compiler based on MLIR and CIRCT☆16Nov 15, 2022Updated 3 years ago
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- ☆13Jul 28, 2022Updated 3 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Mar 13, 2026Updated last week
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 2 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆22Apr 25, 2025Updated 10 months ago
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆20Jan 29, 2026Updated last month
- Processor support packages☆20Feb 2, 2021Updated 5 years ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Jul 4, 2014Updated 11 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Jan 13, 2021Updated 5 years ago
- Header-only C/C++ static keys to avoid the overhead of conditional branches☆14Feb 10, 2024Updated 2 years ago
- AXI X-Bar☆19Apr 8, 2020Updated 5 years ago
- Freecores website☆19Dec 22, 2016Updated 9 years ago
- 平头哥无剑100开源SoC平台（双核E902，安全启动，BootROM，IOPMP，Mailbox，RSA-2048，SHA-2， WS2812，Flash）☆22Sep 2, 2023Updated 2 years ago
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Mar 15, 2026Updated last week
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆37Updated this week
- Provides automation scripts for building BFMs☆16Apr 19, 2025Updated 11 months ago
- ☆15Dec 9, 2025Updated 3 months ago
- ☆16May 10, 2019Updated 6 years ago
- There is segmentation fault of VCS which should be fixed.☆43Sep 19, 2023Updated 2 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆10Feb 11, 2021Updated 5 years ago
- SystemVerilog & Verilog Module I/O parser and printer☆25Jul 25, 2021Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Apr 13, 2023Updated 2 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Mar 15, 2026Updated last week
- A DSL for Linear Temporal Logic + Interface with Z3 for solving☆11Mar 12, 2015Updated 11 years ago
- [WIP] Dockerize Synopsys/Cadence EDA tools☆94Mar 29, 2019Updated 6 years ago
- HMAC-based Extract-and-Expand Key Derivation Function (HKDF) implemented in Python.☆22Jan 17, 2024Updated 2 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆12Jan 17, 2024Updated 2 years ago
- ☆33Nov 25, 2022Updated 3 years ago
- Host software for running SSITH processors on AWS F1 FPGAs☆20Jul 20, 2021Updated 4 years ago
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 6 years ago