Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
☆33Feb 6, 2020Updated 6 years ago
Alternatives and similar repositories for RISC-Verdi
Users that are interested in RISC-Verdi are comparing it to the libraries listed below
Sorting:
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated 9 months ago
- A stream to RTL compiler based on MLIR and CIRCT☆16Nov 15, 2022Updated 3 years ago
- This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol☆13Jul 11, 2018Updated 7 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last week
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 6 years ago
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 2 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated this week
- Used for hardware trojan detection(Based on Trust_Hub)☆10Jul 30, 2019Updated 6 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆12Jan 17, 2024Updated 2 years ago
- ☆15Dec 9, 2025Updated 2 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- ☆12Jul 28, 2022Updated 3 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- A Flexible Cache Architectural Simulator☆16Sep 16, 2025Updated 5 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆33Feb 16, 2026Updated 2 weeks ago
- Nix template for the chisel-based industrial designing flows.☆52Apr 23, 2025Updated 10 months ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Updated this week
- A DSL for Linear Temporal Logic + Interface with Z3 for solving☆11Mar 12, 2015Updated 10 years ago
- ☆16May 10, 2019Updated 6 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆53Jan 31, 2026Updated last month
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Jul 4, 2014Updated 11 years ago
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Updated this week
- Header-only C/C++ static keys to avoid the overhead of conditional branches☆14Feb 10, 2024Updated 2 years ago
- SystemVerilog Extension Library -- a library of utilities for generic programming and increased productivity☆34Jul 27, 2024Updated last year
- My tests and experiments with some popular dl frameworks.☆17Sep 11, 2025Updated 5 months ago
- VCD (Value Change Dump) Tracing for C++☆14Updated this week
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- Provides automation scripts for building BFMs☆16Apr 19, 2025Updated 10 months ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆35Apr 15, 2020Updated 5 years ago
- UVM resource from github, run simulation use YASAsim flow☆33Apr 25, 2020Updated 5 years ago
- [WIP] Dockerize Synopsys/Cadence EDA tools☆94Mar 29, 2019Updated 6 years ago
- C++ SystemC Implementation of a Systolic Array☆16May 15, 2020Updated 5 years ago
- Processor support packages☆19Feb 2, 2021Updated 5 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Apr 7, 2025Updated 10 months ago
- ☆18Jul 9, 2025Updated 7 months ago