Alternatives and similar repositories for RISC-Verdi

Users that are interested in RISC-Verdi are comparing it to the libraries listed below

• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆32Updated last year
• pulp-platform / axi_llc
  ☆32Updated 3 weeks ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆61Updated last year
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated 11 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆43Updated last year
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆53Updated 4 months ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆21Updated 7 months ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• pulp-platform / ace
  ☆20Updated last week
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated last year
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 2 months ago
• atfox272 / AXI4-Interconnect
  RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…
  ☆19Updated 9 months ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆32Updated last week
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆63Updated last week
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆68Updated 10 months ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆52Updated 3 weeks ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆48Updated last year
• antmicro / verilator-verification
  Test dashboard for verification features in Verilator
  ☆28Updated this week
• Xilinx / pcie-model
  PCI Express controller model
  ☆71Updated 3 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆35Updated 4 years ago
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆31Updated 7 years ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆60Updated 3 weeks ago
• sequencer / arithmetic
  ☆33Updated 9 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated 2 weeks ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆72Updated last year
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆20Updated last month
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆71Updated 3 weeks ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated last week