armleo / ArmleoCPU
ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set
☆4Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for ArmleoCPU
- Reconfigurable Binary Engine☆15Updated 3 years ago
- Open FPGA Modules☆23Updated last month
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- Platform Level Interrupt Controller☆35Updated 6 months ago
- Implementation of the PCIe physical layer☆30Updated last week
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆43Updated 2 years ago
- Open source ISS and logic RISC-V 32 bit project☆40Updated last week
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- SoC Based on ARM Cortex-M3☆25Updated 6 months ago
- ☆34Updated 10 months ago
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated last month
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆36Updated last month
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆15Updated 6 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆59Updated last month
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆37Updated 3 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆35Updated 2 years ago
- Network on Chip for MPSoC☆25Updated 3 weeks ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- JTAG Test Access Port (TAP)☆30Updated 10 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆26Updated 3 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆26Updated last month
- APB UVC ported to Verilator☆11Updated last year
- A simple DDR3 memory controller☆51Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆45Updated 3 years ago