armleo / ArmleoCPU
ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set
☆6Updated 2 years ago
Alternatives and similar repositories for ArmleoCPU:
Users that are interested in ArmleoCPU are comparing it to the libraries listed below
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆64Updated last month
- SystemVerilog Functional Coverage for RISC-V ISA☆26Updated 6 months ago
- Open FPGA Modules☆23Updated 5 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 3 years ago
- Platform Level Interrupt Controller☆38Updated 10 months ago
- SystemVerilog Logger☆17Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆48Updated 2 months ago
- APB UVC ported to Verilator☆11Updated last year
- ☆25Updated this week
- Hamming ECC Encoder and Decoder to protect memories☆31Updated 2 months ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated last week
- AXI DMA Check: A utility to measure DMA speeds in simulation☆14Updated 2 months ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- USB -> AXI Debug Bridge☆36Updated 3 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated 2 weeks ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆29Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆33Updated 4 years ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- ☆36Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- General Purpose AXI Direct Memory Access☆48Updated 10 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 10 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆20Updated 6 years ago