ppashakhanloo / verilog-adders
Implementation of different types of adder circuits
☆14Updated 9 years ago
Alternatives and similar repositories for verilog-adders:
Users that are interested in verilog-adders are comparing it to the libraries listed below
- A repository for SystemC Learning examples☆64Updated 2 years ago
- This is a tutorial on standard digital design flow☆73Updated 3 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆47Updated 5 months ago
- 32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…☆24Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆59Updated 5 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆31Updated 2 years ago
- ☆26Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆65Updated last year
- Implementing Different Adder Structures in Verilog☆60Updated 5 years ago
- A verilog implementation for Network-on-Chip☆71Updated 6 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆33Updated 6 months ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆27Updated 4 years ago
- HLS for Networks-on-Chip☆32Updated 3 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆77Updated 5 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- Complete tutorial code.☆15Updated 8 months ago
- 3×3脉动阵列乘法器☆36Updated 5 years ago
- ☆25Updated 4 years ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆85Updated 4 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆60Updated 8 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆27Updated 3 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- ☆24Updated 5 years ago
- course design☆22Updated 6 years ago
- ☆13Updated 5 years ago
- ☆13Updated last year