pgroupATusc / HitGraph
Source code for "HitGraph: High-throughput Graph Processing"
☆10Updated 4 years ago
Alternatives and similar repositories for HitGraph:
Users that are interested in HitGraph are comparing it to the libraries listed below
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- An HBM FPGA based SpMV Accelerator☆13Updated 5 months ago
- Graph accelerator on FPGAs and ASICs☆12Updated 6 years ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆17Updated 2 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- NeuraChip Accelerator Simulator☆11Updated 9 months ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆20Updated 3 months ago
- ☆23Updated 4 years ago
- A Dataflow library for graph analytics acceleration☆14Updated 9 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- HLS project modeling various sparse accelerators.☆12Updated 3 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 2 years ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆16Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆84Updated 4 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- An end-to-end GCN inference accelerator written in HLS☆19Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆20Updated 6 years ago
- ☆34Updated 3 years ago
- ☆26Updated 7 years ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆18Updated 10 months ago
- STONNE Simulator integrated into SST Simulator☆17Updated 10 months ago
- Hybrid Memory Cube Simulation & Research Infrastructure☆15Updated last year
- ☆16Updated 3 years ago
- The programming runtime and interfaces for ARENA.☆14Updated 3 years ago
- Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube☆11Updated 8 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago