pgroupATusc / HitGraph
Source code for "HitGraph: High-throughput Graph Processing"
☆10Updated 4 years ago
Alternatives and similar repositories for HitGraph:
Users that are interested in HitGraph are comparing it to the libraries listed below
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- An HBM FPGA based SpMV Accelerator☆12Updated 7 months ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆17Updated 2 years ago
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Updated 3 years ago
- ☆23Updated 4 years ago
- NeuraChip Accelerator Simulator☆11Updated last year
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆18Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Graph accelerator on FPGAs and ASICs☆12Updated 6 years ago
- ☆26Updated 7 years ago
- An end-to-end GCN inference accelerator written in HLS☆19Updated 3 years ago
- ☆35Updated 4 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆16Updated last year
- STONNE Simulator integrated into SST Simulator☆19Updated last year
- A list of our chiplet simulaters☆32Updated 3 weeks ago
- HLS project modeling various sparse accelerators.☆12Updated 3 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 2 years ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆21Updated 6 years ago
- ☆16Updated 3 years ago
- DASS HLS Compiler☆29Updated last year
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- A Dataflow library for graph analytics acceleration☆14Updated 9 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆20Updated 9 years ago