Altera JTAG UART wrapper for Bluespec
☆26Mar 27, 2014Updated 12 years ago
Alternatives and similar repositories for alterajtaguart
Users that are interested in alterajtaguart are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Python module to interact with an Intel JTAG UART☆18May 8, 2021Updated 5 years ago
- FPGA USB 1.1 Low-Speed Implementation☆36Oct 3, 2018Updated 7 years ago
- How to use the Intel JTAG primitive without using virtual JTAG☆17Oct 31, 2021Updated 4 years ago
- A Grako-based parser for IEEE 1149.1 Boundary-Scan Description Language (BSDL) files☆29Sep 2, 2025Updated 8 months ago
- Finding the bacteria in rotting FPGA designs.☆14Dec 28, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆34Nov 23, 2020Updated 5 years ago
- Direct Python interface to Altera SLD Mega-function☆20Apr 26, 2014Updated 12 years ago
- Python tools to interact with boundary scan-capable devices. Useful for reverse engineering, testing, etc.☆17May 3, 2016Updated 10 years ago
- Numato Opsis Developer Documentation☆13Jan 19, 2019Updated 7 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Feb 24, 2023Updated 3 years ago
- Set up your own CTF with NIZKCTF☆14Oct 20, 2017Updated 8 years ago
- TMDS encoding tools☆18Jan 11, 2018Updated 8 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Jan 7, 2016Updated 10 years ago
- Xilinx Virtual Cable Daemon☆20Nov 20, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Upstream for Non Interactive Zero Knowledge CTF platform☆10May 21, 2020Updated 6 years ago
- Open Source Hardware Designs for working with DisplayPort and intercepting AUX signals.☆20Oct 17, 2019Updated 6 years ago
- Mini CPU design with JTAG UART support☆21Jun 8, 2021Updated 4 years ago
- This is how we interfere with broken AUR packages 🔧☆14Oct 16, 2024Updated last year
- Sending UDP packets out over a Gigabit PHY with an FPGA.☆44May 12, 2016Updated 10 years ago
- ☆15Oct 9, 2021Updated 4 years ago
- Firmware for a Canon DSLR IR remote loaded on an Arduino and an Atmel microcontroller☆11Jan 26, 2018Updated 8 years ago
- Synchronous Message Exchange☆11Feb 3, 2026Updated 3 months ago
- XTRX Software Defined Radio documentation files☆24Jan 3, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Free Libre Open-Source/-Hardware JTAG/UART adapter based on FTDI2232H☆32Dec 12, 2016Updated 9 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆59Mar 16, 2023Updated 3 years ago
- A small 32-bit implementation of the RISC-V architecture☆33Apr 10, 2026Updated last month
- Hardware Description Language Translator☆17May 20, 2026Updated last week
- XVCD implementation for ANITA. Note that "ftdi_xvc_core.c" is a generic libftdi-based MPSSE XVC handler, and is awesome.☆19Jul 10, 2020Updated 5 years ago
- Constrained random stimuli generation for C++ and SystemC☆11Nov 1, 2016Updated 9 years ago
- Propositional Encodings in C++11☆18Sep 6, 2018Updated 7 years ago
- LED blink example design for the Arrow DECA FPGA board☆16Jul 30, 2021Updated 4 years ago
- Some Python scripts to program Xilinx FPGAs using OpenOCD☆24Oct 22, 2016Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- LIB:Library for interacting with an FPGA over USB☆85Jan 16, 2021Updated 5 years ago
- JavaScript action for users to easily install tip/nightly GHDL assets in GitHub Actions workflows☆16Jan 12, 2025Updated last year
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Mar 9, 2020Updated 6 years ago
- POKEY chipmusic editor☆14Apr 17, 2026Updated last month
- ☆16Mar 12, 2024Updated 2 years ago
- Platform Test Edition☆16Mar 11, 2018Updated 8 years ago
- SGMII☆14Jul 17, 2014Updated 11 years ago