thotypous / alterajtaguart
Altera JTAG UART wrapper for Bluespec
☆25Updated 10 years ago
Related projects: ⓘ
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆57Updated last month
- PicoRV☆43Updated 4 years ago
- Virtual JTAG UART for Altera Devices☆45Updated 10 years ago
- FPGA USB 1.1 Low-Speed Implementation☆32Updated 5 years ago
- Board and connector definition files for nMigen☆28Updated 3 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆80Updated 6 years ago
- Nitro USB FPGA core☆82Updated 6 months ago
- Wishbone interconnect utilities☆34Updated 3 months ago
- A repo of basic Verilog/SystemVerilog modules useful in other circuits.☆20Updated 6 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆39Updated 5 months ago
- Using VexRiscv without installing Scala☆34Updated 2 years ago
- Using the TinyFPGA BX USB code in user designs☆49Updated 5 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆47Updated 3 weeks ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆92Updated last year
- 妖刀夢渡☆55Updated 5 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆38Updated 3 years ago
- SDRAM controller with multiple wishbone slave ports☆25Updated 5 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆78Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆34Updated last year
- KiCad Library to make it easy to create both host boards and expansion boards and which are compatible with the Digilent "PMOD" specifica…☆36Updated 3 years ago
- ☆57Updated 11 months ago
- Direct Python interface to Altera SLD Mega-function☆20Updated 10 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆84Updated 4 years ago
- Yosys Plugins☆20Updated 5 years ago
- Minimal DVI / HDMI Framebuffer☆74Updated 4 years ago
- Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chil…☆37Updated this week
- This repository contains iCEBreaker examples for Amaranth HDL.☆36Updated 10 months ago
- Project X-Ray Database: XC7 Series☆63Updated 2 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆58Updated 5 years ago
- Change part number or package in a Xilinx 7-series FPGA bitstream☆36Updated 4 years ago