Altera JTAG UART wrapper for Bluespec
☆26Mar 27, 2014Updated 12 years ago
Alternatives and similar repositories for alterajtaguart
Users that are interested in alterajtaguart are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Python module to interact with an Intel JTAG UART☆17May 8, 2021Updated 5 years ago
- FPGA USB 1.1 Low-Speed Implementation☆36Oct 3, 2018Updated 7 years ago
- How to use the Intel JTAG primitive without using virtual JTAG☆17Oct 31, 2021Updated 4 years ago
- A Grako-based parser for IEEE 1149.1 Boundary-Scan Description Language (BSDL) files☆29Sep 2, 2025Updated 10 months ago
- Finding the bacteria in rotting FPGA designs.☆14Dec 28, 2020Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Direct Python interface to Altera SLD Mega-function☆20Apr 26, 2014Updated 12 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆34Nov 23, 2020Updated 5 years ago
- Simple SoC in VHDL with full toolchain and custom board.☆28Jun 4, 2018Updated 8 years ago
- Python tools to interact with boundary scan-capable devices. Useful for reverse engineering, testing, etc.☆17May 3, 2016Updated 10 years ago
- Numato Opsis Developer Documentation☆13Jan 19, 2019Updated 7 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Feb 24, 2023Updated 3 years ago
- TMDS encoding tools☆18Jan 11, 2018Updated 8 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆25Jan 7, 2016Updated 10 years ago
- Open Source Hardware Designs for working with DisplayPort and intercepting AUX signals.☆20Oct 17, 2019Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Xilinx Virtual Cable Daemon☆20Nov 20, 2019Updated 6 years ago
- Create database files for the genealogytree LaTeX package from GEDCOM files☆11May 21, 2026Updated 2 months ago
- Sending UDP packets out over a Gigabit PHY with an FPGA.☆45May 12, 2016Updated 10 years ago
- Firmware for a Canon DSLR IR remote loaded on an Arduino and an Atmel microcontroller☆11Jan 26, 2018Updated 8 years ago
- Example code for the Numato Opsis board, the first HDMI2USB production board.☆58Apr 27, 2018Updated 8 years ago
- XVCD implementation for ANITA. Note that "ftdi_xvc_core.c" is a generic libftdi-based MPSSE XVC handler, and is awesome.☆19Jul 10, 2020Updated 6 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆61Mar 16, 2023Updated 3 years ago
- XTRX Software Defined Radio documentation files☆24Jan 3, 2020Updated 6 years ago
- Free Libre Open-Source/-Hardware JTAG/UART adapter based on FTDI2232H☆32Dec 12, 2016Updated 9 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Design and Verification of a Complete Application Specific Integrated Circuit☆12Nov 21, 2016Updated 9 years ago
- Hardware transactions library for Amaranth☆30Updated this week
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 8 years ago
- A small 32-bit implementation of the RISC-V architecture☆34Apr 10, 2026Updated 3 months ago
- Hardware Description Language Translator☆17Jun 9, 2026Updated last month
- Some Python scripts to program Xilinx FPGAs using OpenOCD☆25Oct 22, 2016Updated 9 years ago
- LIB:Library for interacting with an FPGA over USB☆85Jan 16, 2021Updated 5 years ago
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Mar 9, 2020Updated 6 years ago
- Sweet32 32bit MRISC CPU - VHDL and software toolchain sources (including documentation)☆38Oct 29, 2015Updated 10 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- OpenOCD remote_bitbang protocol implemented on the Teensy 3.2 via USB serial☆18Feb 29, 2016Updated 10 years ago
- SGMII☆14Jul 17, 2014Updated 12 years ago
- Yosys plugin for synthesis of Bluespec code☆16Sep 8, 2021Updated 4 years ago
- a small simple slow serial FPGA core☆16Mar 11, 2021Updated 5 years ago
- ☆26Aug 30, 2020Updated 5 years ago
- IEC 62056 smart meter readout in perl☆11Mar 16, 2018Updated 8 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Jun 8, 2017Updated 9 years ago