patc15 / mipscpu
☆33Updated this week
Related projects: ⓘ
- educational microarchitectures for risc-v isa☆64Updated 5 years ago
- ☆21Updated 3 years ago
- The RTL source for AnyCore RISC-V☆29Updated 2 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆70Updated 8 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 7 years ago
- Lipsi: Probably the Smallest Processor in the World☆81Updated 5 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆61Updated 2 months ago
- Tests for example Rocket Custom Coprocessors☆68Updated 4 years ago
- ☆31Updated 7 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆38Updated 4 years ago
- A Simple As Possible RISCV-32I core with debug module.☆43Updated 4 years ago
- A template for building new projects/platforms using the BOOM core.☆24Updated 5 years ago
- Platform Level Interrupt Controller☆34Updated 4 months ago
- Support for Rocket Chip on Zynq FPGAs☆39Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆45Updated 4 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆48Updated 4 years ago
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆21Updated last year
- ☆12Updated 3 years ago
- ☆23Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆48Updated last month
- RISCV model for Verilator/FPGA targets☆44Updated 4 years ago
- SystemC training aimed at TLM.☆24Updated 4 years ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆12Updated 5 months ago
- A Tiny Processor Core☆99Updated last week
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- RISC-V Formal Verification Framework☆95Updated 4 months ago
- ☆42Updated 2 years ago
- A vector processor implemented in Chisel☆21Updated 10 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆87Updated 5 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆17Updated 5 years ago
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago