Alternatives and similar repositories for ADMS

Users that are interested in ADMS are comparing it to the libraries listed below

• rubund / graywolf
  ☆114Updated 5 years ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆128Updated this week
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆53Updated 3 years ago
• DDD-FIT-CTU / CMOS-SPICE-Model-Collections
  MOSIS MPW Test Data and SPICE Models Collections
  ☆39Updated 5 years ago
• idea-fasoc / fasoc
  ☆56Updated 2 years ago
• dwarning / VA-Models
  Verilog-A simulation models
  ☆91Updated 3 months ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆89Updated last year
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated 2 months ago
• skuep / GDS3D
  Fork from https://sourceforge.net/projects/gds3d
  ☆68Updated last year
• imr / ngspice
  mirror of ngspice repo at git://git.code.sf.net/p/ngspice/ngspice ngspice-ngspice
  ☆225Updated this week
• Lenty / SLiCAP_python
  Open-source version of SLiCAP, implemented in python
  ☆37Updated last year
• chipfoundry / volare
  Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
  ☆75Updated 2 months ago
• ggventurini / python-deltasigma
  A port of the MATLAB Delta Sigma Toolbox based on free software and very little sleep
  ☆95Updated 3 years ago
• aidangoettsch / asg
  An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.
  ☆29Updated 5 years ago
• ediloren / FastCap2
  FastCap is the premium capacitance solver originally developed at M.I.T. on Unix platform. A de-facto golden reference standard, FastCap …
  ☆52Updated 10 years ago
• google / sky90fd-pdk
  ☆122Updated 2 years ago
• eskiyerli / revolution-eda
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆59Updated last week
• capn-freako / PyBERT
  Serial communication link bit error rate tester simulator, written in Python.
  ☆120Updated this week
• RTimothyEdwards / XCircuit
  XCircuit circuit drawing and schematic capture tool
  ☆138Updated 2 months ago
• mbalestrini / gdsiistl
  Converts GDSII files to STL files.
  ☆42Updated 2 years ago
• pascalkuthe / OpenVAF
  An innovative Verilog-A compiler
  ☆178Updated last year
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆69Updated 2 months ago
• iic-jku / osic-multitool
  JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
  ☆77Updated 10 months ago
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆223Updated last year
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆39Updated 4 years ago
• Qucs / qucsator
  Circuit simulator of the Qucs project
  ☆31Updated last month
• mabrains / sky130_klayout_pdk
  Skywater 130nm Klayout Device Generators PDK
  ☆30Updated last year
• jonpry / Pill
  Skill language interpreter
  ☆73Updated 5 years ago
• wrcad / xictools
  XicTools: Xic graphical editor, WRspice circuit simulator, and accessories. for electronic design.
  ☆180Updated 2 months ago