Alternatives and similar repositories for cascade

Users that are interested in cascade are comparing it to the libraries listed below

• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆374Updated 2 years ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆328Updated 3 years ago
• f32c / f32c
  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
  ☆412Updated 2 weeks ago
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆242Updated 5 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆616Updated 3 years ago
• dawsonjon / Chips-2.0
  FPGA Design Suite based on C to Verilog design flow.
  ☆246Updated 6 years ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆749Updated last year
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆202Updated 4 years ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆456Updated last month
• openpower-cores / a2i
  ☆247Updated 3 years ago
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆399Updated last month
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆563Updated 2 months ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,125Updated 3 weeks ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆873Updated 5 years ago
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆431Updated 3 weeks ago
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆836Updated 5 months ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆352Updated 2 weeks ago
• phanrahan / magma
  magma circuits
  ☆263Updated last year
• antonblanchard / microwatt
  A tiny Open POWER ISA softcore written in VHDL 2008
  ☆701Updated last month
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆679Updated 3 years ago
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆974Updated 5 months ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆316Updated last week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆479Updated last week
• grahamedgecombe / icicle
  32-bit RISC-V system on chip for iCE40 FPGAs
  ☆310Updated 2 years ago
• Domipheus / TPU
  TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…
  ☆150Updated 9 years ago
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆683Updated this week
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆282Updated last year
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆742Updated last month
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆747Updated last week
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆600Updated 2 years ago