Alternatives and similar repositories for cascade

Users that are interested in cascade are comparing it to the libraries listed below

• dawsonjon / Chips-2.0
  FPGA Design Suite based on C to Verilog design flow.
  ☆245Updated 6 years ago
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆203Updated 4 years ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆327Updated 3 years ago
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆240Updated 2 months ago
• f32c / f32c
  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
  ☆413Updated last month
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆375Updated last year
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆607Updated 3 years ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆431Updated last month
• openpower-cores / a2i
  ☆247Updated 2 years ago
• phanrahan / magma
  magma circuits
  ☆261Updated 9 months ago
• Domipheus / TPU
  TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…
  ☆148Updated 9 years ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆549Updated 2 weeks ago
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆423Updated 3 months ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆312Updated 2 weeks ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆214Updated last year
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆393Updated 9 months ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆871Updated 5 years ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 8 months ago
• cornell-brg / pymtl
  Python-based hardware modeling framework
  ☆242Updated 5 years ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆748Updated 11 months ago
• antonblanchard / microwatt
  A tiny Open POWER ISA softcore written in VHDL 2008
  ☆691Updated this week
• grahamedgecombe / icicle
  32-bit RISC-V system on chip for iCE40 FPGAs
  ☆309Updated 2 years ago
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆602Updated 2 years ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,091Updated 5 months ago
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆816Updated 2 months ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆340Updated 2 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆155Updated 3 years ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆168Updated 4 years ago
• MoonbaseOtago / vroom
  VRoom! RISC-V CPU
  ☆508Updated 11 months ago