A Just-In-Time Compiler for Verilog from VMware Research
☆446Jul 1, 2021Updated 5 years ago
Alternatives and similar repositories for cascade
Users that are interested in cascade are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆106Jun 27, 2022Updated 4 years ago
- A Just-In-Time Compiler for Verilog from VMware Research☆23Dec 14, 2020Updated 5 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆463Jun 20, 2026Updated last week
- Build Customized FPGA Implementations for Vivado☆382Updated this week
- A hardware compiler based on LLHD and CIRCT☆270Jun 30, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- XLS: Accelerated HW Synthesis☆1,503Updated this week
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆238Updated this week
- Yosys Open SYnthesis Suite☆4,553Updated this week
- Low Level Hardware Description — A foundation for building hardware design tools.☆434Apr 20, 2022Updated 4 years ago
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆103Nov 22, 2019Updated 6 years ago
- A low-level intermediate representation for hardware description languages☆28Jun 28, 2020Updated 6 years ago
- ☆247Aug 12, 2022Updated 3 years ago
- Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…☆1,423Jun 18, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SystemVerilog to Verilog conversion☆739Mar 28, 2026Updated 3 months ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- Time-sensitive affine types for predictable hardware generation☆152Jan 5, 2026Updated 5 months ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 3 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- An abstraction library for interfacing EDA tools☆774Updated this week
- A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen☆687Jan 8, 2022Updated 4 years ago
- Bluespec Compiler (BSC)☆1,123Updated this week
- FPGA Assembly (FASM) Parser and Generator☆102Jul 25, 2022Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- nMigen examples for the ULX3S board☆16Nov 30, 2020Updated 5 years ago
- SystemVerilog compiler and language services☆1,078Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆379Updated this week
- A modern hardware definition language and toolchain based on Python☆2,037May 25, 2026Updated last month
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- Rust proof-of-concept for GPU waveform rendering☆13Jul 22, 2020Updated 5 years ago
- Mutation Cover with Yosys (MCY)☆93Jun 2, 2026Updated last month
- Documenting the Xilinx 7-series bit-stream format.☆897Jun 5, 2025Updated last year
- draws an SVG schematic from a JSON netlist☆800Jan 25, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,877Jun 22, 2026Updated last week
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated last year
- Package manager and build abstraction tool for FPGA/ASIC development☆1,426Jun 17, 2026Updated 2 weeks ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,020Updated this week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,241Jun 25, 2026Updated last week
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆121May 14, 2025Updated last year
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆225Jun 22, 2026Updated last week