Alternatives and similar repositories for cascade

Users that are interested in cascade are comparing it to the libraries listed below

• dawsonjon / Chips-2.0
  FPGA Design Suite based on C to Verilog design flow.
  ☆246Updated 6 years ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆374Updated 2 years ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆328Updated 3 years ago
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆202Updated 5 years ago
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆433Updated last month
• f32c / f32c
  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
  ☆412Updated last month
• openpower-cores / a2i
  ☆247Updated 3 years ago
• cornell-brg / pymtl
  Python-based hardware modeling framework
  ☆245Updated 6 years ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆459Updated last week
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆242Updated 6 months ago
• grahamedgecombe / icicle
  32-bit RISC-V system on chip for iCE40 FPGAs
  ☆312Updated 2 years ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆619Updated 3 years ago
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆839Updated 6 months ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆876Updated 5 years ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆567Updated 3 months ago
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆402Updated 2 months ago
• antonblanchard / microwatt
  A tiny Open POWER ISA softcore written in VHDL 2008
  ☆705Updated 2 months ago
• phanrahan / magma
  magma circuits
  ☆263Updated last year
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆319Updated last month
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 6 years ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆748Updated last year
• m-labs / misoc
  The original high performance and small footprint system-on-chip based on Migen™
  ☆339Updated 2 weeks ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆481Updated last week
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆679Updated 3 years ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆353Updated last month
• jhallen / vivado_setup
  How to set up Xilinx Vivado for source control
  ☆108Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆235Updated last year
• MoonbaseOtago / vroom
  VRoom! RISC-V CPU
  ☆514Updated last year
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆600Updated 2 years ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆176Updated 2 years ago