vmware-archive / cascade
A Just-In-Time Compiler for Verilog from VMware Research
☆436Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for cascade
- Flexible Intermediate Representation for RTL☆731Updated 3 months ago
- RISC-V Formal Verification Framework☆585Updated 2 years ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆889Updated this week
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆357Updated last year
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆310Updated 2 years ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,004Updated 2 months ago
- Documenting the Xilinx 7-series bit-stream format.☆774Updated this week
- Small footprint and configurable DRAM core☆382Updated last month
- Package manager and build abstraction tool for FPGA/ASIC development☆1,206Updated 2 weeks ago
- ☆244Updated 2 years ago
- VHDL synthesis (based on ghdl)☆308Updated 4 months ago
- A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen☆661Updated 2 years ago
- FPGA Design Suite based on C to Verilog design flow.☆235Updated 5 years ago
- Documenting the Lattice ECP5 bit-stream format.☆399Updated 9 months ago
- An abstraction library for interfacing EDA tools☆645Updated this week
- VeeR EH1 core☆822Updated last year
- A directory of Western Digital’s RISC-V SweRV Cores☆857Updated 4 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆497Updated last month
- A small, light weight, RISC CPU soft core☆1,305Updated last month
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆201Updated 3 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆230Updated last week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆624Updated this week
- VHDL compiler and simulator☆636Updated this week
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆218Updated 11 months ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆407Updated 2 weeks ago
- 32-bit RISC-V system on chip for iCE40 FPGAs☆301Updated last year
- The root repo for lowRISC project and FPGA demos.☆597Updated last year
- The OpenPiton Platform☆643Updated last month
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆368Updated last week