A Just-In-Time Compiler for Verilog from VMware Research
☆446Jul 1, 2021Updated 5 years ago
Alternatives and similar repositories for cascade
Users that are interested in cascade are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆106Jun 27, 2022Updated 4 years ago
- A Just-In-Time Compiler for Verilog from VMware Research☆22Dec 14, 2020Updated 5 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆473Updated this week
- Build Customized FPGA Implementations for Vivado☆385Updated this week
- A hardware compiler based on LLHD and CIRCT☆270Jun 30, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆240Updated this week
- XLS: Accelerated HW Synthesis☆1,847Updated this week
- Yosys Open SYnthesis Suite☆4,721Updated this week
- Low Level Hardware Description — A foundation for building hardware design tools.☆437Apr 20, 2022Updated 4 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆103Nov 22, 2019Updated 6 years ago
- A low-level intermediate representation for hardware description languages☆28Jun 28, 2020Updated 6 years ago
- Flexible Intermediate Representation for RTL☆747Aug 20, 2024Updated 2 years ago
- SystemVerilog to Verilog conversion☆749Aug 18, 2026Updated 2 weeks ago
- Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…☆1,430Aug 23, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆247Aug 12, 2022Updated 4 years ago
- 👾 Design ∪ Hardware☆79Jul 1, 2026Updated 2 months ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- Time-sensitive affine types for predictable hardware generation☆152Jan 5, 2026Updated 7 months ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 4 years ago
- A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen☆688Jan 8, 2022Updated 4 years ago
- Bluespec Compiler (BSC)☆1,142Aug 24, 2026Updated last week
- An abstraction library for interfacing EDA tools☆790Aug 12, 2026Updated 2 weeks ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- FPGA Assembly (FASM) Parser and Generator☆103Jul 25, 2022Updated 4 years ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- A modern hardware definition language and toolchain based on Python☆2,074Aug 23, 2026Updated last week
- Test suite designed to check compliance with the SystemVerilog standard.☆390Updated this week
- SystemVerilog compiler and language services☆1,124Updated this week
- Rust proof-of-concept for GPU waveform rendering☆13Jul 22, 2020Updated 6 years ago
- nMigen examples for the ULX3S board☆16Nov 30, 2020Updated 5 years ago
- Documenting the Xilinx 7-series bit-stream format.☆909Jun 5, 2025Updated last year
- Mutation Cover with Yosys (MCY)☆97Aug 5, 2026Updated 3 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- draws an SVG schematic from a JSON netlist☆821Jan 25, 2024Updated 2 years ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,037Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,453Aug 24, 2026Updated last week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,923Updated this week
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated 2 years ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,259Updated this week
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆122May 14, 2025Updated last year