Alternatives and similar repositories for snap

Users that are interested in snap are comparing it to the libraries listed below

• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆73Updated last year
• OPAE / intel-fpga-bbb
  Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  ☆104Updated 11 months ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆88Updated 3 years ago
• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆134Updated 4 years ago
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆116Updated last month
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆176Updated 2 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 7 months ago
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆172Updated this week
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆114Updated 2 years ago
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆87Updated 3 months ago
• OFS / opae-sdk
  Open Programmable Acceleration Engine
  ☆268Updated 5 months ago
• sangwoojun / bluespecpcie
  PCIe library for the Xilinx 7 series FPGAs in the Bluespec language
  ☆82Updated 3 years ago
• fpgasystems / caribou
  Caribou: Distributed Smart Storage built with FPGAs
  ☆68Updated 7 years ago
• pcie-bench / pciebench-netfpga
  pcie-bench code for NetFPGA/VCU709 cards
  ☆43Updated 7 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆145Updated last year
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆52Updated 2 years ago
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆50Updated 9 years ago
• StanfordVLSI / Genesis2
  A home for Genesis2 sources.
  ☆44Updated 6 months ago
• Xilinx / xup_vitis_network_example
  VNx: Vitis Network Examples
  ☆156Updated 4 months ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆220Updated 5 years ago
• Xilinx / open-nic-driver
  AMD OpenNIC driver includes the Linux kernel driver
  ☆71Updated last year
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 4 years ago
• Xilinx / SDAccel-Tutorials
  SDAccel Development Environment Tutorials
  ☆109Updated 5 years ago
• CMU-SAFARI / SoftMC
  SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…
  ☆143Updated 2 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 8 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆182Updated 8 months ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆64Updated 2 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆106Updated 7 years ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆354Updated last week
• KastnerRG / spector
  Spector: An OpenCL FPGA Benchmark Suite
  ☆49Updated 6 years ago