Alternatives and similar repositories for snap:

Users that are interested in snap are comparing it to the libraries listed below

• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆68Updated 5 months ago
• OPAE / intel-fpga-bbb
  Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  ☆104Updated 3 weeks ago
• sangwoojun / bluespecpcie
  PCIe library for the Xilinx 7 series FPGAs in the Bluespec language
  ☆73Updated 2 years ago
• ibm-capi / pslse
  Power Service Layer Simulation Engine
  ☆28Updated 3 years ago
• Xilinx / open-nic-driver
  AMD OpenNIC driver includes the Linux kernel driver
  ☆64Updated last month
• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆124Updated 3 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆85Updated 2 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated last year
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆149Updated last year
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆132Updated 4 months ago
• fpgasystems / davos
  Distributed Accelerator OS
  ☆61Updated 2 years ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆302Updated last week
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆78Updated 4 years ago
• Xilinx / SDAccel-Tutorials
  SDAccel Development Environment Tutorials
  ☆108Updated 4 years ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆119Updated 2 years ago
• KastnerRG / spector
  Spector: An OpenCL FPGA Benchmark Suite
  ☆44Updated 6 years ago
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆107Updated last month
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆99Updated last year
• fpgasystems / caribou
  Caribou: Distributed Smart Storage built with FPGAs
  ☆65Updated 6 years ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆113Updated 2 months ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆164Updated last year
• Xilinx / xup_vitis_network_example
  VNx: Vitis Network Examples
  ☆141Updated 6 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆46Updated 8 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆101Updated 2 years ago
• oprecomp / DDR4_controller
  ☆53Updated 4 years ago
• Xilinx / PYNQ-Networking
  Networking Overlay on PYNQ
  ☆48Updated 5 years ago
• nvdla / vp
  Virtual Platform for NVDLA
  ☆142Updated 6 years ago
• sbates130272 / capi-textswap
  A "Hello World" for the Power8 CAPI Interface. Includes application C and RTL code.
  ☆18Updated 9 years ago