ibm-capi / pslse
Power Service Layer Simulation Engine
☆28Updated 3 years ago
Alternatives and similar repositories for pslse:
Users that are interested in pslse are comparing it to the libraries listed below
- A "Hello World" for the Power8 CAPI Interface. Includes application C and RTL code.☆18Updated 9 years ago
- Library to abstract the userspace cxl (CAPI) Linux kernel API☆35Updated 4 years ago
- AFU framework for streaming applications with CAPI.☆13Updated 7 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 2 months ago
- CAPI SNAP Framework Hardware and Software☆110Updated 3 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆68Updated 7 months ago
- AMD OpenNIC driver includes the Linux kernel driver☆65Updated 2 months ago
- ☆23Updated 3 years ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆124Updated 3 years ago
- ☆85Updated 2 years ago
- QEMU libsystemctlm-soc co-simulation demos.☆141Updated 10 months ago
- For publishing the source for UG1352 "Get Moving with Alveo"☆51Updated 4 years ago
- Open Programmable Acceleration Engine☆262Updated 3 weeks ago
- Support for Rocket Chip on Zynq FPGAs☆40Updated 5 years ago
- This repo contains the Limago code☆80Updated 2 years ago
- A wrapper for the SPEC CPU2006 benchmark suite.☆88Updated 3 years ago
- SDAccel Development Environment Tutorials☆108Updated 4 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆49Updated 6 years ago
- Connectal is a framework for software-driven hardware development.☆166Updated last year
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆101Updated 2 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- Spector: An OpenCL FPGA Benchmark Suite☆45Updated 6 years ago
- VNx: Vitis Network Examples☆145Updated 8 months ago
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆81Updated 5 months ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆252Updated 2 weeks ago
- Benchmarks for Accelerator Design and Customized Architectures☆120Updated 5 years ago