HanPU-Code / CNN_YOLO_AI_accelerator
This project is to design yolo AI accelerator in verilog HDL.
☆14Updated 7 months ago
Alternatives and similar repositories for CNN_YOLO_AI_accelerator
Users that are interested in CNN_YOLO_AI_accelerator are comparing it to the libraries listed below
Sorting:
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- 使用FPGA实现CNN模型☆15Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆15Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆31Updated 2 years ago
- DMA controller for CNN accelerator☆13Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆11Updated 9 months ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated last year
- Verilog and matlab implementation of tanh using Cordic algorithm☆9Updated 4 years ago
- ☆10Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆34Updated last year
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆11Updated 2 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆24Updated 3 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- This repository contains full code of Softmax Layer in Verilog☆18Updated 4 years ago
- ☆15Updated last year
- Router 1 x 3 verilog implementation☆13Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆32Updated 4 years ago
- ☆14Updated 2 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆14Updated 8 months ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆16Updated 9 months ago