This project is to design yolo AI accelerator in verilog HDL.
☆34Oct 8, 2024Updated last year
Alternatives and similar repositories for CNN_YOLO_AI_accelerator
Users that are interested in CNN_YOLO_AI_accelerator are comparing it to the libraries listed below
Sorting:
- IC设计中的一些经典书籍☆13Jul 28, 2020Updated 5 years ago
- AI assisted Shell, aka "Ash". Wraps around your existing shell and brings AI-LLM to the CLI for analyzing EDA files.☆28Updated this week
- 东秦第五届龙芯班仓库☆10Oct 22, 2023Updated 2 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆13May 9, 2022Updated 3 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆22Jun 30, 2025Updated 8 months ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆34Aug 22, 2024Updated last year
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆17Feb 27, 2021Updated 5 years ago
- Assembly Line Balancing with Hierarchical Worker Assignment☆11Jan 22, 2021Updated 5 years ago
- An Assortment of Convolutional Neural Networks☆11Mar 10, 2019Updated 7 years ago
- Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-b…☆18Nov 18, 2025Updated 4 months ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated last year
- Hardware Acceleration of Neural Networks for Event Camera-Based Object Detection on SoC FPGAs☆21Aug 31, 2025Updated 6 months ago
- [Applied Intelligence 2022] Python code for ACP☆12Sep 5, 2023Updated 2 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆18Jul 9, 2024Updated last year
- yolov5-acceleration-fpga☆11Jun 25, 2025Updated 8 months ago
- Measure the performance of three modulation techniques using PAPR, spectral efficiency, BER☆19Feb 28, 2017Updated 9 years ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆33Jun 30, 2021Updated 4 years ago
- An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)☆76Jun 7, 2012Updated 13 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- RIME A physics based optimization algorithm, Neurocomputing, 2023 https://doi.org/10.1016/j.neucom.2023.02.010, This paper proposes an ef…☆21Aug 9, 2024Updated last year
- Hardware and software implementation of Sparsely-active SNNs☆22Mar 6, 2026Updated 2 weeks ago
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆17May 30, 2023Updated 2 years ago
- 2023年全国大学生集成电路创 新创业大赛-海运捷讯杯-全国二等奖作品 FPGA-Based SSD-MobileNet Acceleator; CNN Acceleator; China IC Competition☆20Dec 2, 2024Updated last year
- study uvm step by step☆11Mar 28, 2019Updated 6 years ago
- Custom YOLOv4 for apple recognition (clean/damaged) on Alveo U280 accelerator card using Vitis AI framework.☆15Nov 1, 2021Updated 4 years ago
- RISC-V-based many-core neuromorphic architecture☆16Aug 3, 2025Updated 7 months ago
- Hardware Accelerators on FPGA for Computer Vision Applications☆12Dec 16, 2025Updated 3 months ago
- 基于FPGA的FFT☆19Feb 18, 2019Updated 7 years ago
- ☆14Mar 24, 2022Updated 3 years ago
- 基4booth乘法器设计与验证☆15Apr 28, 2024Updated last year
- unsigned Radix-2 SRT division,基2除法☆16May 12, 2015Updated 10 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- Scraping repository of the most relevant topics with regards to Spatio-Temporal Neural Networks available in the arXiv archive. The repos…☆15Updated this week
- 一个JPEG有损图像压缩编码器☆13May 22, 2023Updated 2 years ago
- Course Project for High Level Chip Design （高层次芯片设计）☆17Jan 2, 2025Updated last year
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆26Jan 2, 2025Updated last year
- Quantization (QAT) Demo on CIFAR10☆17Jan 29, 2024Updated 2 years ago
- 使用DDS芯片AD9914产生线性扫频信号☆12Dec 9, 2020Updated 5 years ago