HanPU-Code / CNN_YOLO_AI_acceleratorLinks
This project is to design yolo AI accelerator in verilog HDL.
☆16Updated 7 months ago
Alternatives and similar repositories for CNN_YOLO_AI_accelerator
Users that are interested in CNN_YOLO_AI_accelerator are comparing it to the libraries listed below
Sorting:
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- 使用FPGA实现CNN模型☆15Updated 5 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆36Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆31Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆14Updated 10 months ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆16Updated 6 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- ☆16Updated last year
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- DMA controller for CNN accelerator☆13Updated 8 years ago
- This repository contains full code of Softmax Layer in Verilog☆18Updated 4 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆17Updated 9 months ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆33Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆10Updated 5 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆11Updated 2 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- ☆10Updated 4 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- ☆10Updated 3 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆73Updated 3 months ago
- ☆15Updated last year
- Nuclei E203 with yolo accelerator based on xc7k325☆14Updated 10 months ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆48Updated 3 months ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆58Updated 3 months ago
- ☆33Updated 6 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago