vipinkmenon / SpatialFilter
☆53Updated 7 months ago
Alternatives and similar repositories for SpatialFilter:
Users that are interested in SpatialFilter are comparing it to the libraries listed below
- Convolutional Neural Network Implemented in Verilog for System on Chip☆26Updated 5 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆54Updated 2 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- 3 layern artificial ANN to recognize handwritten digits and implement in FPGA☆8Updated 3 years ago
- ☆16Updated 10 months ago
- Architectural design of data router in verilog☆29Updated 5 years ago
- ☆16Updated last year
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆141Updated 8 months ago
- To develop Arm Cortex-M0 based SoCs, from creating high-level functional specifications to design, implementation and testing on FPGA pla…☆24Updated 4 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆15Updated 9 months ago
- AXI DMA 32 / 64 bits☆106Updated 10 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated last year
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- UVM Testbench to verify serial transmission of data between SPI master and slave☆41Updated 4 years ago
- ☆39Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- UVM and System Verilog Manuals☆39Updated 6 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆57Updated last year
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆24Updated 2 years ago
- A verilog implementation for Network-on-Chip☆71Updated 7 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆134Updated 4 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆58Updated 6 months ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆38Updated 7 months ago
- AXI Interconnect☆47Updated 3 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆48Updated 4 years ago
- APB to I2C☆39Updated 10 years ago