vipinkmenon / SpatialFilterLinks
☆62Updated last year
Alternatives and similar repositories for SpatialFilter
Users that are interested in SpatialFilter are comparing it to the libraries listed below
Sorting:
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆171Updated last year
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated last year
- ☆37Updated 6 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆38Updated 3 years ago
- Lecture about FIR filter on an FPGA☆12Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆68Updated last year
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆27Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- Implementing Different Adder Structures in Verilog☆76Updated 6 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆25Updated 7 years ago
- Final project for Computer Architecture FA16☆19Updated 8 years ago
- Verilog implementation of a pre-trained handwritten digit recognition simple neural network.☆25Updated last year
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆40Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆70Updated 5 years ago
- ☆16Updated last year
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆24Updated last year
- ☆22Updated 2 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆56Updated 2 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- ☆54Updated 6 years ago
- How to Accelerate an Image Upscaling CNN on FPGA Using HLS☆24Updated 4 years ago
- A 2D convolution hardware implementation written in Verilog☆50Updated 4 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆17Updated last year
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆53Updated 8 years ago