Alternatives and similar repositories for sonata-system

Users that are interested in sonata-system are comparing it to the libraries listed below

• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆111Updated this week
• newaetech / sonata-pcb
  Design files and associated documentation for Sonata PCB, part of the Sunburst Project
  ☆18Updated 2 months ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆106Updated last week
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆96Updated this week
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆54Updated last month
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆51Updated 5 months ago
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆72Updated this week
• riscv / riscv-aia
  ☆89Updated 3 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆146Updated 7 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆83Updated 6 months ago
• polarfire-soc / hart-software-services
  PolarFire SoC hart software services
  ☆43Updated 3 weeks ago
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆34Updated 3 weeks ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆101Updated this week
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆32Updated this week
• riscvarchive / riscv-code-size-reduction
  ☆149Updated last year
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆52Updated this week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated last month
• antmicro / rowhammer-tester
  ☆63Updated last month
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• riscv-software-src / riscof
  ☆83Updated 2 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆33Updated last year
• riscv-non-isa / riscv-semihosting
  ☆30Updated this week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆119Updated last week
• hex-five / multizone-sdk
  MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…
  ☆85Updated last year
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆114Updated 8 months ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 7 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆141Updated last week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆61Updated 5 months ago
• five-embeddev / riscv-scratchpad
  RISC-V Scratchpad
  ☆68Updated 2 years ago