Alternatives and similar repositories for sonata-system

Users that are interested in sonata-system are comparing it to the libraries listed below

• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆113Updated last month
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆112Updated 2 months ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆112Updated this week
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆81Updated this week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆194Updated last month
• newaetech / sonata-pcb
  Design files and associated documentation for Sonata PCB, part of the Sunburst Project
  ☆18Updated 6 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated 2 weeks ago
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆116Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 11 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆25Updated last year
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆83Updated last week
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆84Updated 9 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 2 months ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆57Updated last month
• riscvarchive / riscv-CMOs
  ☆90Updated last month
• riscv-non-isa / riscv-semihosting
  ☆32Updated this week
• riscv-software-src / riscof
  ☆92Updated last month
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆88Updated 2 months ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆52Updated 9 months ago
• hex-five / multizone-sdk
  MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…
  ☆86Updated last year
• embench / embench-iot
  The main Embench repository
  ☆290Updated last year
• riscv-software-src / riscv-ctg
  ☆41Updated 10 months ago
• five-embeddev / riscv-scratchpad
  RISC-V Scratchpad
  ☆71Updated 2 years ago
• riscv / riscv-aia
  ☆96Updated last month
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆323Updated 3 weeks ago
• olofk / corescore
  CoreScore
  ☆163Updated last month
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆138Updated 2 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆150Updated this week
• polarfire-soc / hart-software-services
  PolarFire SoC hart software services
  ☆47Updated last month