lowRISC / sonata-systemLinks
A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
☆45Updated 2 weeks ago
Alternatives and similar repositories for sonata-system
Users that are interested in sonata-system are comparing it to the libraries listed below
Sorting:
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆112Updated last week
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆107Updated this week
- Design files and associated documentation for Sonata PCB, part of the Sunburst Project☆18Updated 3 months ago
- HW Design Collateral for Caliptra RoT IP☆99Updated last week
- ☆89Updated 3 months ago
- Raptor end-to-end FPGA Compiler and GUI☆83Updated 7 months ago
- This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…☆72Updated 2 weeks ago
- ☆63Updated 2 months ago
- Naive Educational RISC V processor☆84Updated last month
- ☆86Updated 3 years ago
- RISC-V Processor Trace Specification☆187Updated 2 weeks ago
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆27Updated 4 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆146Updated 8 months ago
- ☆101Updated last week
- RISC-V IOMMU Specification☆123Updated this week
- ☆30Updated 3 weeks ago
- FPGA tool performance profiling☆102Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆109Updated last month
- The multi-core cluster of a PULP system.☆104Updated last week
- RISC-V Nexus Trace TG documentation and reference code☆51Updated 6 months ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆25Updated last year
- RISC-V Scratchpad☆68Updated 2 years ago
- This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…☆52Updated last week
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆54Updated this week
- Bare metal example software projects for PolarFire SoC☆34Updated 4 months ago
- Building and deploying container images for open source electronic design automation (EDA)☆115Updated 9 months ago
- MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…☆85Updated last year
- Side-channel analysis setup for OpenTitan☆35Updated last month
- PolarFire SoC hart software services☆45Updated 3 weeks ago
- RISC-V Architecture Profiles☆154Updated 5 months ago