xupgit / Advanced-Embedded-System-Design-Flow-on-Zynq
☆52Updated 5 years ago
Alternatives and similar repositories for Advanced-Embedded-System-Design-Flow-on-Zynq:
Users that are interested in Advanced-Embedded-System-Design-Flow-on-Zynq are comparing it to the libraries listed below
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆84Updated last year
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆50Updated last year
- PYNQ Composabe Overlays☆70Updated 9 months ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆60Updated 7 months ago
- RTL Verilog library for various DSP modules☆85Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- AMD University Program HLS tutorial☆81Updated 4 months ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 3 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆93Updated 4 years ago
- FFT generator using Chisel☆58Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆138Updated last month
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆82Updated 5 years ago
- AXI总线连接器☆96Updated 4 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆144Updated 9 months ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆16Updated last year
- ☆86Updated last year
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- Pipeline FFT Implementation in Verilog HDL☆102Updated 5 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- Verilog digital signal processing components☆129Updated 2 years ago
- ☆190Updated 2 months ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆147Updated 5 years ago
- round robin arbiter☆70Updated 10 years ago