xupgit / Advanced-Embedded-System-Design-Flow-on-ZynqLinks
☆52Updated 6 years ago
Alternatives and similar repositories for Advanced-Embedded-System-Design-Flow-on-Zynq
Users that are interested in Advanced-Embedded-System-Design-Flow-on-Zynq are comparing it to the libraries listed below
Sorting:
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆84Updated last year
- PYNQ Composabe Overlays☆73Updated last year
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆54Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- AMD University Program HLS tutorial☆97Updated 7 months ago
- FFT generator using Chisel☆60Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆33Updated 3 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- ☆65Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 10 months ago
- A verilog FPGA Interface for AXI4_Lite from Slave side☆10Updated 5 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆62Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆162Updated 5 years ago
- AHB DMA 32 / 64 bits☆56Updated 10 years ago
- AXI DMA 32 / 64 bits☆113Updated 10 years ago
- ☆34Updated 6 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆85Updated 6 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆55Updated 4 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆59Updated last year
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆154Updated last year
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆62Updated last year
- Pipeline FFT Implementation in Verilog HDL☆120Updated 6 years ago