Alternatives and similar repositories for FPGA-Design-Flow-using-Vivado

Users that are interested in FPGA-Design-Flow-using-Vivado are comparing it to the libraries listed below

• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆85Updated 2 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• Avnet / bdf
  Avnet Board Definition Files
  ☆136Updated 2 months ago
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆179Updated 6 years ago
• xupgit / Advanced-Embedded-System-Design-Flow-on-Zynq
  ☆54Updated 6 years ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆108Updated 3 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆182Updated this week
• k0nze / zedboard_axi4_master_burst_example
  Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)
  ☆44Updated 8 years ago
• Xilinx / XilinxBoardStore
  ☆306Updated 2 weeks ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆144Updated 11 years ago
• raysalemi / Python4RTLVerification
  ☆170Updated 3 years ago
• Xilinx / xup_fpga_vivado_flow
  AMD Xilinx University Program Vivado tutorial
  ☆42Updated 2 years ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆67Updated 3 years ago
• Xilinx / Vivado-Design-Tutorials
  ☆237Updated 3 months ago
• ivanvig / 2dconv-FPGA
  A 2D convolution hardware implementation written in Verilog
  ☆51Updated 4 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆159Updated 3 years ago
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆115Updated last month
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆76Updated 6 years ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆157Updated 2 months ago
• Marco-Winzker / FPGA-Vision
  Learn about image processing with an FPGA. Video lectures explain algorithm and implementation of lane detection for automotive driving. …
  ☆44Updated last year
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆67Updated 8 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆161Updated 6 years ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆111Updated 2 years ago
• Digilent / digilent-vivado-scripts
  ☆69Updated 4 months ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 3 weeks ago
• xfguo / tbgen
  Generate testbench for your verilog module.
  ☆38Updated 7 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆182Updated last year
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆95Updated 6 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆81Updated 4 years ago