wjc852456 / Neural-Networks-on-SiliconLinks
This is a collection of works on neural networks and neural accelerators.
☆40Updated 6 years ago
Alternatives and similar repositories for Neural-Networks-on-Silicon
Users that are interested in Neural-Networks-on-Silicon are comparing it to the libraries listed below
Sorting:
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆31Updated 6 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆139Updated 5 years ago
- ☆14Updated 5 years ago
- ☆71Updated 5 years ago
- MAESTRO binary release☆22Updated 5 years ago
- MAERI public release☆31Updated 3 years ago
- Simulator for BitFusion☆100Updated 4 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- research, experimentation and implementation of hardware-agnostic accelerated DL framework☆36Updated this week
- Residual Binarized Neural Network☆43Updated 7 years ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆216Updated 6 years ago
- ☆40Updated 5 years ago
- Official implementation of "Searching for Winograd-aware Quantized Networks" (MLSys'20)☆27Updated last year
- pytorch fixed point training tool/framework☆34Updated 4 years ago
- ☆58Updated 5 years ago
- ☆33Updated 6 years ago
- Approximate layers - TensorFlow extension☆27Updated last month
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆51Updated 7 years ago
- ☆45Updated 5 years ago
- first-order deep learning accelerator model☆18Updated 7 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 6 years ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- A general framework for optimizing DNN dataflow on systolic array☆36Updated 4 years ago
- ☆71Updated 2 years ago
- Reproduction of WAGE in PyTorch.☆42Updated 6 years ago
- Python code to show how a systolic array works. Written for https://medium.com/@antonpaquin/whats-inside-a-tpu-c013eb51973e☆28Updated 6 years ago