wjc852456 / Neural-Networks-on-SiliconLinks
This is a collection of works on neural networks and neural accelerators.
☆40Updated 6 years ago
Alternatives and similar repositories for Neural-Networks-on-Silicon
Users that are interested in Neural-Networks-on-Silicon are comparing it to the libraries listed below
Sorting:
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆141Updated 5 years ago
- ☆14Updated 5 years ago
- first-order deep learning accelerator model☆19Updated 7 years ago
- Jupyter notebook examples on image classification with quantized neural networks☆69Updated 5 years ago
- Residual Binarized Neural Network☆43Updated 7 years ago
- pytorch fixed point training tool/framework☆34Updated 4 years ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆221Updated 6 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆90Updated 6 years ago
- ☆71Updated 5 years ago
- Approximate layers - TensorFlow extension☆27Updated 5 months ago
- MAESTRO binary release☆22Updated 5 years ago
- ☆60Updated 5 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆93Updated 6 years ago
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆55Updated 7 years ago
- ☆119Updated 7 years ago
- A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacemen…☆18Updated 7 years ago
- MAERI public release☆31Updated 4 years ago
- An implementation of a BinaryConnect network for cifar10☆11Updated 5 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆20Updated 5 years ago
- Simulator for BitFusion☆101Updated 5 years ago
- ☆44Updated 5 years ago
- ☆90Updated 5 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆20Updated 7 years ago
- Binary Neural Network on IceStick FPGA.☆53Updated 7 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- Codes for Binary Ensemble Neural Network: More Bits per Network or More Networks per Bit?☆31Updated 5 years ago
- ☆34Updated 6 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆12Updated 9 years ago