QDucasse / nn_benchmarkLinks
🧠 Benchmark facility to train networks on different datasets for PyTorch/Brevitas
☆26Updated 2 years ago
Alternatives and similar repositories for nn_benchmark
Users that are interested in nn_benchmark are comparing it to the libraries listed below
Sorting:
- SAMO: Streaming Architecture Mapping Optimisation☆33Updated last year
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆57Updated 3 years ago
- ☆58Updated 5 years ago
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆24Updated 3 years ago
- Approximate layers - TensorFlow extension☆27Updated 2 months ago
- ☆71Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- ☆30Updated 7 months ago
- DAC System Design Contest 2020☆29Updated 5 years ago
- Vitis HLS Library for FINN☆198Updated 3 weeks ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- Low Precision(quantized) Yolov5☆39Updated 3 months ago
- Jupyter notebook examples on image classification with quantized neural networks☆69Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks.☆24Updated last year
- ☆94Updated last year
- ☆82Updated last year
- ☆17Updated 2 years ago
- A collection of tutorials for the fpgaConvNet framework.☆41Updated 9 months ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 4 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆143Updated last month
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆16Updated 3 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- An FPGA Accelerator for Transformer Inference☆83Updated 3 years ago