bonfireprocessor / bonfire-cpuLinks
FPGA optimized RISC-V (RV32IM) implemenation
☆34Updated 4 years ago
Alternatives and similar repositories for bonfire-cpu
Users that are interested in bonfire-cpu are comparing it to the libraries listed below
Sorting:
- SoftCPU/SoC engine-V☆55Updated 6 months ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆46Updated 7 months ago
- Yet Another RISC-V Implementation☆97Updated last year
- Wishbone interconnect utilities☆41Updated 8 months ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆106Updated last month
- ☆34Updated 4 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- LatticeMico32 soft processor☆107Updated 11 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- FuseSoC standard core library☆147Updated 4 months ago
- Naive Educational RISC V processor☆88Updated 2 months ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- ☆86Updated last week
- Spen's Official OpenOCD Mirror☆50Updated 7 months ago
- A utility for Composing FPGA designs from Peripherals☆185Updated 9 months ago
- OpenFPGA☆34Updated 7 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆95Updated 5 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆62Updated 6 years ago
- Demo SoC for SiliconCompiler.☆61Updated last week
- ☆42Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆67Updated 3 weeks ago
- User-friendly explanation of Yosys options☆112Updated 4 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆54Updated 2 weeks ago