bonfireprocessor / bonfire-cpu
FPGA optimized RISC-V (RV32IM) implemenation
☆34Updated 4 years ago
Alternatives and similar repositories for bonfire-cpu:
Users that are interested in bonfire-cpu are comparing it to the libraries listed below
- SoftCPU/SoC engine-V☆54Updated 2 weeks ago
- Wishbone interconnect utilities☆39Updated last month
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆68Updated 2 years ago
- Spen's Official OpenOCD Mirror☆48Updated 3 weeks ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆50Updated 2 months ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆86Updated 6 years ago
- Reusable Verilog 2005 components for FPGA designs☆40Updated last month
- JTAG DPI module for OpenRISC simulation with Verilator☆17Updated 12 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆89Updated 6 months ago
- Naive Educational RISC V processor☆79Updated 5 months ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆53Updated this week
- Project X-Ray Database: XC7 Series☆66Updated 3 years ago
- A padring generator for ASICs☆25Updated last year
- Open Processor Architecture☆26Updated 8 years ago
- ☆41Updated 4 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆40Updated 3 months ago
- Xilinx Unisim Library in Verilog☆75Updated 4 years ago
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- ☆33Updated 4 years ago
- Documenting the Lattice ECP5 bit-stream format.☆54Updated last year
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆62Updated 7 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆47Updated this week
- OpenRISC processor IP core based on Tomasulo algorithm☆31Updated 3 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆74Updated 6 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆44Updated 2 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 8 months ago
- Demo SoC for SiliconCompiler.☆59Updated 3 weeks ago
- Bitstream relocation and manipulation tool.☆44Updated 2 years ago