bonfireprocessor / bonfire-cpuLinks
FPGA optimized RISC-V (RV32IM) implemenation
☆34Updated 5 years ago
Alternatives and similar repositories for bonfire-cpu
Users that are interested in bonfire-cpu are comparing it to the libraries listed below
Sorting:
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- Featherweight RISC-V implementation☆53Updated 4 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆93Updated 7 years ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated this week
- Yet Another RISC-V Implementation☆99Updated last year
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆92Updated 6 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆72Updated 7 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Wishbone interconnect utilities☆44Updated last month
- Spen's Official OpenOCD Mirror☆51Updated 10 months ago
- ☆34Updated 5 years ago
- ☆63Updated 7 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 4 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 7 years ago
- An Open Source configuration of the Arty platform☆131Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆70Updated last month
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆83Updated 5 years ago
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 6 years ago
- Naive Educational RISC V processor☆94Updated 3 months ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Updated 6 years ago
- Bitstream relocation and manipulation tool.☆51Updated 3 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆59Updated 2 months ago
- FPGA USB 1.1 Low-Speed Implementation☆35Updated 7 years ago
- Docker Development Environment for SpinalHDL☆20Updated last year
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- LatticeMico32 soft processor☆107Updated 11 years ago