bonfireprocessor / bonfire-cpu
FPGA optimized RISC-V (RV32IM) implemenation
☆34Updated 4 years ago
Alternatives and similar repositories for bonfire-cpu:
Users that are interested in bonfire-cpu are comparing it to the libraries listed below
- SoftCPU/SoC engine-V☆54Updated last year
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Wishbone interconnect utilities☆38Updated 8 months ago
- Spen's Official OpenOCD Mirror☆48Updated 10 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆67Updated 2 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 6 months ago
- ☆32Updated 3 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Open Processor Architecture☆26Updated 8 years ago
- A padring generator for ASICs☆24Updated last year
- ☆40Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆39Updated last year
- FPGA based microcomputer sandbox for software and RTL experimentation☆52Updated last week
- Yet Another RISC-V Implementation☆86Updated 4 months ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆26Updated 6 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆84Updated 6 years ago
- Experimental flows using nextpnr for Xilinx devices☆41Updated last month
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- PicoRV☆44Updated 4 years ago
- A pipelined RISC-V processor☆50Updated last year
- Yosys Plugins☆21Updated 5 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆49Updated 2 weeks ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆82Updated 4 months ago
- Project X-Ray Database: XC7 Series☆65Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆36Updated 3 years ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- Documenting the Lattice ECP5 bit-stream format.☆53Updated last year
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆58Updated 6 years ago