muneebullashariff / i2c_vipLinks
Verification IP for I2C protocol
☆49Updated 4 years ago
Alternatives and similar repositories for i2c_vip
Users that are interested in i2c_vip are comparing it to the libraries listed below
Sorting:
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆130Updated 7 years ago
- Verification IP for APB protocol☆72Updated 4 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆101Updated 2 years ago
- a very simple risc_cpu verification demo with uvm☆26Updated 6 years ago
- UVM AHB VIP☆87Updated 2 months ago
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆32Updated 5 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆46Updated 5 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆26Updated 3 years ago
- ☆43Updated 2 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆37Updated 5 years ago
- UART design in SV and verification using UVM and SV☆50Updated 5 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆51Updated 5 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆56Updated 5 years ago
- An uvm verification env for ahb2apb bridge☆56Updated 4 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 4 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆156Updated 5 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆112Updated 10 months ago
- ☆23Updated 4 years ago
- UVM examples and projects☆148Updated 4 months ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆36Updated 2 years ago
- VIP for AXI Protocol☆157Updated 3 years ago
- generate UVM testbench using python☆28Updated 7 years ago
- UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…☆16Updated 10 months ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆110Updated 7 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆21Updated last year
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆64Updated 2 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆150Updated 7 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆132Updated 4 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆184Updated 7 years ago
- AXI Interconnect☆54Updated 4 years ago