zhangmozhe / microshift_compression

Related projects ⓘ

Alternatives and complementary repositories for microshift_compression

• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆32Updated 4 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆52Updated 5 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆25Updated 6 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆58Updated 4 years ago
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆29Updated 3 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆41Updated 2 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆54Updated 4 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 6 months ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆48Updated 7 years ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 2 years ago
• Aperture-Electronic / Realtime-Bicubic-16X-SuperResolution-IP
  APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS
  ☆24Updated last year
• sh-vlad / FPGA_rtime_HDR_video
  We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.
  ☆31Updated 5 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆32Updated 3 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆35Updated 3 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆28Updated last month
• samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IP
  It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
  ☆16Updated 4 years ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆17Updated 6 years ago
• srohit0 / CORDIC
  CORDIC VLSI-IP for deep learning activation functions
  ☆13Updated 5 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆59Updated 3 years ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 10 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆26Updated 3 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆78Updated 5 years ago
• freecores / video_stream_scaler
  Video Stream Scaler
  ☆40Updated 10 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆31Updated 6 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• ivanvig / 2dconv-FPGA
  A 2D convolution hardware implementation written in Verilog
  ☆42Updated 3 years ago
• armleo / ArmleoCPU
  ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set
  ☆4Updated 2 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆83Updated 2 years ago
• adki / RTL-Design-For-FPGA
  Engineering Program on RTL Design for FPGA Accelerator
  ☆26Updated 4 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago