zhangmozhe / microshift_compression
Microshift Compression: An Efficient Image Compression Algorithm for Hardware
☆32Updated 4 years ago
Alternatives and similar repositories for microshift_compression:
Users that are interested in microshift_compression are comparing it to the libraries listed below
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- SoC Based on ARM Cortex-M3☆30Updated this week
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- USB -> AXI Debug Bridge☆36Updated 3 years ago
- ☆15Updated 6 years ago
- APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS☆22Updated 2 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- ☆25Updated 3 years ago
- CORDIC VLSI-IP for deep learning activation functions☆14Updated 5 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆13Updated 7 months ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆29Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- Simple single-port AXI memory interface☆41Updated 11 months ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- SDRAM controller with AXI4 interface☆92Updated 5 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- EE 287 2012 Fall☆30Updated 12 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- This is a circular buffer controller used in FPGA.☆33Updated 9 years ago