zEko / GestureRecognition_VerilogLinks
Identifies ASL Hand Gesture for numbers using image processing in verilog
☆14Updated 13 years ago
Alternatives and similar repositories for GestureRecognition_Verilog
Users that are interested in GestureRecognition_Verilog are comparing it to the libraries listed below
Sorting:
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆43Updated last year
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 4 years ago
- AHB DMA 32 / 64 bits☆56Updated 10 years ago
- AHB Bus lite v3.0☆16Updated 5 years ago
- APB to I2C☆41Updated 10 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 5 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆32Updated 3 years ago
- uvm auto generator☆23Updated 6 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆55Updated 3 years ago
- ☆25Updated 4 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆25Updated 8 years ago
- SPI interface connect to APB BUS with Verilog HDL☆31Updated 4 years ago
- AXI Interconnect☆49Updated 3 years ago
- Verification IP for APB protocol☆66Updated 4 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 10 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆56Updated last year
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆16Updated 5 years ago
- ☆36Updated 9 years ago
- ☆20Updated 2 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 3 years ago
- Verification IP for APB protocol☆26Updated 4 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆55Updated 8 years ago
- Reed Solomon Decoder (204,188)☆12Updated 10 years ago