smartfoxdata / axi4lite_gpio
General purpose IO port with AXI4-Lite interface
☆11Updated 2 months ago
Alternatives and similar repositories for axi4lite_gpio:
Users that are interested in axi4lite_gpio are comparing it to the libraries listed below
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆88Updated last year
- UVM Testbench to verify serial transmission of data between SPI master and slave☆44Updated 4 years ago
- Verification IP for I2C protocol☆41Updated 3 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆113Updated 7 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- UVM examples and projects☆131Updated 6 years ago
- VIP for AXI Protocol☆131Updated 2 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆58Updated last year
- ☆43Updated 3 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆27Updated 6 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆38Updated 4 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆148Updated 5 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆49Updated 4 years ago
- UVM AHB VIP☆83Updated 5 months ago
- A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology☆101Updated 11 years ago
- UART design in SV and verification using UVM and SV☆43Updated 5 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆101Updated 3 months ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆168Updated 6 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆120Updated 3 years ago
- UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…☆10Updated 4 months ago
- Verification IP for APB protocol☆62Updated 4 years ago
- An uvm verification env for ahb2apb bridge☆50Updated 4 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆32Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆31Updated 2 years ago
- a very simple risc_cpu verification demo with uvm☆22Updated 5 years ago
- Synchronous FIFO Testbench☆10Updated 3 years ago
- SystemVerilog VIP for AMBA APB protocol☆72Updated 3 years ago
- UVM agents☆78Updated 7 years ago
- AHB to APB Bridge VIP☆29Updated 6 years ago
- Examples and reference for System Verilog Assertions☆83Updated 8 years ago