General purpose IO port with AXI4-Lite interface
☆10Feb 7, 2025Updated last year
Alternatives and similar repositories for axi4lite_gpio
Users that are interested in axi4lite_gpio are comparing it to the libraries listed below
Sorting:
- uvm_starter is a simple template for starting uvm projects☆11Feb 11, 2025Updated last year
- uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol☆21Feb 7, 2025Updated last year
- uvm_axi is a uvm package for modeling and verifying AXI protocol☆21Feb 7, 2025Updated last year
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆32Feb 7, 2025Updated last year
- A simple implementation about LEGv8 instruction set using Verilog HDL.☆11May 8, 2022Updated 3 years ago
- A simple program to convert gdsII files to vector output formats. Currently used to create laser-cut models of standard cells.☆12May 30, 2023Updated 2 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- KASIRGA - GUN | RV32IMCX☆11Aug 14, 2024Updated last year
- Using python, selenium to get real photo paths and download them.☆11Aug 7, 2017Updated 8 years ago
- Parametric GPIO Peripheral☆12Jan 30, 2025Updated last year
- Summer School Week 1 & 2 repo☆12Jul 1, 2022Updated 3 years ago
- This is a 4*5 PE array for LeNet accelerator based on FPGA.☆13Jul 20, 2022Updated 3 years ago
- A Pandora Radio Client that also saves music to disk☆17Oct 26, 2015Updated 10 years ago
- 包括同步FIFO（输入输出位宽相同），异步FIFO（输入输出位宽相同），异步FIFO（能实现输出数据 位宽是输入数据位宽的1/2或2倍）☆23Nov 7, 2022Updated 3 years ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated 7 months ago
- Maven Silicon Project☆20Oct 13, 2018Updated 7 years ago
- A python project to automatically generate the UVM testbench document.☆21Feb 27, 2024Updated 2 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Nov 7, 2018Updated 7 years ago
- Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…☆21Apr 13, 2023Updated 2 years ago
- ☆26Sep 3, 2025Updated 6 months ago
- ☆24Dec 8, 2021Updated 4 years ago
- a very simple risc_cpu verification demo with uvm☆26Apr 28, 2019Updated 6 years ago
- DDR3 function verification environment in UVM☆26Apr 1, 2018Updated 7 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 4 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆31Oct 9, 2020Updated 5 years ago
- Software for high density electrophysiology☆30Jan 24, 2025Updated last year
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Aug 28, 2023Updated 2 years ago
- Contains commonly used UVM components (agents, environments and tests).☆32Aug 17, 2018Updated 7 years ago
- Top-level repository for the ACT EDA flow☆38Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆149Updated this week
- A small utility to download images from gettyimages☆37Jul 15, 2020Updated 5 years ago
- Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.☆41Jul 24, 2024Updated last year
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Jun 14, 2018Updated 7 years ago
- This store contains Configurable Example Designs.☆51Feb 26, 2026Updated last week
- ☆39Apr 10, 2023Updated 2 years ago
- Mirror of tachyon-da cvc Verilog simulator☆48Jul 16, 2023Updated 2 years ago
- Verification IP for I2C protocol☆52Sep 22, 2021Updated 4 years ago
- Converts GDSII files to STL files.☆42Dec 12, 2023Updated 2 years ago
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆51May 24, 2020Updated 5 years ago