xiesicong / fpga_sobel_ov5640_hdmiLinks
fpga跑sobel识别算法
☆36Updated 4 years ago
Alternatives and similar repositories for fpga_sobel_ov5640_hdmi
Users that are interested in fpga_sobel_ov5640_hdmi are comparing it to the libraries listed below
Sorting:
- FPGA实现简单的图像处理算法☆46Updated 2 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆48Updated 5 years ago
- FPGA图像处理仿真平台☆26Updated 3 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆33Updated 2 years ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛(高云赛道)项目,题目基于高云FPGA的多路网络视频监控编码系统。☆47Updated last year
- The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…☆39Updated last year
- fpga读取摄像头数据上传到上位机,720P@60Hz☆20Updated 4 years ago
- 帧差法运动目标检测,基于ZYNQ7020☆67Updated 3 years ago
- 基于FPGA和ov5640的实时图像采集及灰度转换系统☆16Updated last year
- MNIST using tensorflow, c++ and fpga (zynq7010)☆25Updated 2 years ago
- ☆62Updated 2 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- 这是我所开发的两个项目,包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆92Updated 7 years ago
- FFT implement by verilog_测试验证已通过☆58Updated 8 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆180Updated 7 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- 基于FPGA的三速以太网UDP协议栈设计☆27Updated last year
- In this project, Canny edge detection, one of the efficient edge detection algorithms is implemented on a Zedboard FPGA using verilog. Th…☆19Updated 3 years ago
- FPGA实现动态图像识别☆22Updated 4 years ago
- 该作品为2024年FPGA创新设计大赛(上海安路科技赛道)国一作品☆20Updated 5 months ago
- The Dark Channel Prior technique is implemented on FPGA using only Verilog code and no Intellectual Property, making it convenient to rep…☆39Updated last year
- 视频旋转(2019FPGA大赛)☆34Updated 5 years ago
- 2023集创赛紫光同创杯一等奖项目☆117Updated last year
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- AXI总线连接器☆99Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 10 months ago
- SPI interface connect to APB BUS with Verilog HDL☆31Updated 3 years ago
- AXI Interconnect☆49Updated 3 years ago
- ☆36Updated 9 years ago
- 使用FPGA实现CNN模型☆15Updated 6 years ago