crboth / LDPC_DecoderLinks
Low Density Parity Check Decoder
☆18Updated 9 years ago
Alternatives and similar repositories for LDPC_Decoder
Users that are interested in LDPC_Decoder are comparing it to the libraries listed below
Sorting:
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆76Updated 2 years ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆52Updated 8 years ago
- Wi-Fi LDPC codec Verilog IP core☆18Updated 6 years ago
- Gaussian noise generator Verilog IP core☆32Updated 2 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆11Updated 4 years ago
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 5 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆57Updated last year
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆124Updated last year
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆23Updated 5 years ago
- Verilog实现OFDM基带☆44Updated 9 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆66Updated 3 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Updated 5 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆54Updated 2 years ago
- Verilog based BCH encoder/decoder☆125Updated 3 years ago
- DVB-S2 LDPC Decoder☆28Updated 11 years ago
- use Verilog HDL implemente bicubic interpolation in FPGA☆27Updated 5 years ago
- Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS☆28Updated 4 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Updated 6 years ago
- A collection of phase locked loop (PLL) related projects☆111Updated last year
- Open FPGA Modules☆24Updated last year
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆59Updated 6 years ago
- Hardware Viterbi Decoder in verilog☆28Updated 6 years ago
- IEEE 802.11 OFDM-based transceiver system☆39Updated 7 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆47Updated last year
- Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..☆41Updated 6 years ago
- My code repositry for common use.☆23Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆108Updated 2 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago