russdill / bch_verilogLinks
Verilog based BCH encoder/decoder
☆123Updated 2 years ago
Alternatives and similar repositories for bch_verilog
Users that are interested in bch_verilog are comparing it to the libraries listed below
Sorting:
- Fully parametrizable combinatorial parallel LFSR/CRC module☆157Updated 6 months ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Verilog digital signal processing components☆155Updated 2 years ago
- UART -> AXI Bridge☆62Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 5 years ago
- SDRAM controller with AXI4 interface☆97Updated 6 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆59Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆138Updated 2 years ago
- PCIE 5.0 Graduation project (Verification Team)☆79Updated last year
- ☆78Updated 3 years ago
- AHB3-Lite Interconnect☆92Updated last year
- A collection of phase locked loop (PLL) related projects☆108Updated last year
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆61Updated 3 years ago
- Pipeline FFT Implementation in Verilog HDL☆132Updated 6 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆115Updated 3 years ago
- Hardware Assisted IEEE 1588 IP Core☆30Updated 11 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆37Updated last year
- I2C controller core☆47Updated 2 years ago
- Ethernet 10GE MAC☆45Updated 11 years ago
- 10G Low Latency Ethernet☆59Updated 2 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆65Updated last month
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year