russdill / bch_verilogLinks
Verilog based BCH encoder/decoder
☆122Updated 2 years ago
Alternatives and similar repositories for bch_verilog
Users that are interested in bch_verilog are comparing it to the libraries listed below
Sorting:
- Fully parametrizable combinatorial parallel LFSR/CRC module☆151Updated 4 months ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- UART -> AXI Bridge☆61Updated 4 years ago
- Verilog digital signal processing components☆143Updated 2 years ago
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 5 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆37Updated 4 years ago
- A collection of phase locked loop (PLL) related projects☆107Updated last year
- Generic FIFO implementation with optional FWFT☆59Updated 5 years ago
- AHB3-Lite Interconnect☆89Updated last year
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆61Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆105Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- JPEG Encoder Verilog☆76Updated 2 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆131Updated last year
- ☆69Updated 3 years ago
- Pipeline FFT Implementation in Verilog HDL☆122Updated 6 years ago
- Fixed Point Math Library for Verilog☆134Updated 10 years ago
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- Verilog UART☆173Updated 12 years ago
- 10G Low Latency Ethernet☆56Updated 2 years ago
- I2C controller core☆47Updated 2 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆56Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- round robin arbiter☆74Updated 10 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- Mathematical Functions in Verilog☆93Updated 4 years ago
- ☆70Updated 3 years ago