Alternatives and similar repositories for bch_verilog

Users that are interested in bch_verilog are comparing it to the libraries listed below

• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆160Updated 10 months ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆69Updated 4 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆100Updated 6 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆115Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆168Updated 3 years ago
• WangXuan95 / FPGA-Gzip-compressor
  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …
  ☆147Updated 2 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 6 years ago
• antmicro / nvme-verilog-pcie
  ☆80Updated 3 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆68Updated 5 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆62Updated 3 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆61Updated 5 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆102Updated 5 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆117Updated 4 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆108Updated last year
• freecores / ha1588
  Hardware Assisted IEEE 1588 IP Core
  ☆30Updated 11 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆76Updated 2 months ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆51Updated 6 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆97Updated last year
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆60Updated 6 months ago
• cjhonlyone / NandFlashController
  AXI Interface Nand Flash Controller (Sync mode)
  ☆99Updated last year
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆78Updated 13 years ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆45Updated 11 years ago
• raysalemi / Python4RTLVerification
  ☆174Updated 3 years ago
• benreynwar / fft-dit-fpga
  Verilog module for calculation of FFT.
  ☆191Updated 13 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆153Updated 6 years ago
• ttchisholm / 10g-low-latency-ethernet
  10G Low Latency Ethernet
  ☆91Updated 2 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆39Updated 4 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆35Updated 9 years ago
• freecores / i2c
  I2C controller core
  ☆47Updated 3 years ago