KevinHexin / FPGA-Bicubic-interpolationView external linksLinks
use Verilog HDL implemente bicubic interpolation in FPGA
☆30Dec 31, 2019Updated 6 years ago
Alternatives and similar repositories for FPGA-Bicubic-interpolation
Users that are interested in FPGA-Bicubic-interpolation are comparing it to the libraries listed below
Sorting:
- Video Stream Scaler☆40Jul 17, 2014Updated 11 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- Bilinear interpolation realizes image scaling based on FPGA☆30Jul 11, 2020Updated 5 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- A verilog parser☆19Apr 12, 2024Updated last year
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆29Nov 3, 2025Updated 3 months ago
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 8 years ago
- FPGA video scaler running on Intel Arria 10☆12May 28, 2019Updated 6 years ago
- ☆33Nov 24, 2025Updated 2 months ago
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆15Feb 18, 2025Updated 11 months ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆13Sep 9, 2022Updated 3 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47May 10, 2024Updated last year
- Automatically exported from code.google.com/p/bicubic-interpolation-image-processing☆10Jan 27, 2016Updated 10 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 9 years ago
- Huffman encoding core (Vivado HLS Project)☆12Oct 15, 2019Updated 6 years ago
- ☆17Jun 5, 2024Updated last year
- A complete Linux project for the ZYBO. This project helps me during my first steps with embedded Linux. You can find anything necessary t…☆13Oct 8, 2020Updated 5 years ago
- ZPU Evo(lution), an enhanced ZPU microprocessor design in VHDL to embed within an FPGA including SoC functionality. Project currently use…☆15Sep 4, 2022Updated 3 years ago
- System Verilog and Emulation. Written all the five channels.☆35Mar 9, 2017Updated 8 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Dec 24, 2024Updated last year
- git clone of http://code.google.com/p/axi-bfm/☆19May 21, 2013Updated 12 years ago
- ☆18Apr 5, 2015Updated 10 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Sep 2, 2023Updated 2 years ago
- CNN accelerator using NoC architecture☆17Dec 6, 2018Updated 7 years ago
- Low Density Parity Check Decoder☆18Sep 12, 2016Updated 9 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆21Feb 4, 2025Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆18Nov 13, 2025Updated 3 months ago
- ☆14Nov 5, 2017Updated 8 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Feb 27, 2025Updated 11 months ago
- APB Logic☆23Jan 22, 2026Updated 3 weeks ago
- This is a circular buffer controller used in FPGA.☆34Jan 12, 2016Updated 10 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆37Oct 25, 2020Updated 5 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Mar 15, 2018Updated 7 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆39Jan 15, 2024Updated 2 years ago
- ☆16Apr 21, 2019Updated 6 years ago