Wi-Fi LDPC codec Verilog IP core
☆19Oct 20, 2019Updated 6 years ago
Alternatives and similar repositories for wifi_ldpc_codec
Users that are interested in wifi_ldpc_codec are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Gaussian noise generator Verilog IP core☆34May 22, 2023Updated 3 years ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆55Sep 17, 2017Updated 8 years ago
- LDPC编码解码matlab代码和Verilog代码及资料☆51Aug 27, 2018Updated 7 years ago
- Playground for implementing LDPC codes on FPGA☆17Jan 1, 2023Updated 3 years ago
- Error Correction Code Transformer☆57Dec 5, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆35Mar 25, 2022Updated 4 years ago
- A min-sum LDPC decoder written in SystemVerilog (IEEE 1800-2012)☆13Jan 8, 2021Updated 5 years ago
- 5G LDPC simulation based on MEX function.☆25Jul 24, 2018Updated 7 years ago
- There are the documents, floating and fixed-point algorithms, and Verilog codes for the project.☆11Jun 27, 2016Updated 9 years ago
- FPGAandLAN☆29Jun 13, 2021Updated 4 years ago
- ☆18Sep 16, 2020Updated 5 years ago
- Automatically exported from code.google.com/p/asy4cn☆11Jul 11, 2022Updated 3 years ago
- Network Tap based on the ZedBoard and Ethernet FMC☆15May 12, 2026Updated 2 weeks ago
- Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..☆44May 2, 2019Updated 7 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Finding the bacteria in rotting FPGA designs.☆14Dec 28, 2020Updated 5 years ago
- An attempt to synthesize GPS signals in FPGA logic.☆20Feb 17, 2026Updated 3 months ago
- ☆13Feb 8, 2021Updated 5 years ago
- 最小和算法实现☆10Jul 12, 2020Updated 5 years ago
- Solutions to the Google foobar challenges made to me☆12Jun 6, 2022Updated 3 years ago
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆61May 11, 2026Updated 2 weeks ago
- FPGA implementation of an ADAT receiver/transmitter using amaranth HDL☆13Sep 17, 2024Updated last year
- Low Density Parity Check codes encoder and decoder, in particular for CCSDS standards.☆67Oct 16, 2018Updated 7 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆22Oct 31, 2017Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- fpga for utrasound mobile device☆13Aug 10, 2015Updated 10 years ago
- Verilog FPGA code : including experimental DSP audio processor☆13Dec 1, 2020Updated 5 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Source and Hardware file of PE1005S camera Module interfacing with Cypress FX3 USB 3.0☆22Feb 9, 2020Updated 6 years ago
- FPGA video scaler running on Intel Arria 10☆12May 28, 2019Updated 7 years ago
- The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)☆10Jan 9, 2016Updated 10 years ago
- Gateware for the Terasic/Arrow DECA board, to become a USB2 high speed audio interface☆22Feb 28, 2022Updated 4 years ago
- RedPitaya application: Software Defined Radio (SDR) for an 8-channel WSPR receiver.☆10Jan 29, 2018Updated 8 years ago
- hdmi-ts Project☆13Jun 11, 2017Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Hardware Description Language Translator☆19May 20, 2026Updated last week
- Vivado design for basic NeTV2 FPGA with chroma-based overlay☆20Dec 24, 2016Updated 9 years ago
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 5 years ago
- Example Codes for Snorkeling in Verilog Bay☆17Sep 9, 2016Updated 9 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 11 years ago
- 4 channel 1GS/s DDS (AD9910 or AD9912 variant)☆17Jul 7, 2025Updated 10 months ago
- Zedboard projects☆11May 15, 2016Updated 10 years ago