Wi-Fi LDPC codec Verilog IP core
☆20Jun 30, 2026Updated last month
Alternatives and similar repositories for wifi_ldpc_codec
Users that are interested in wifi_ldpc_codec are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Gaussian noise generator Verilog IP core☆34Jul 5, 2026Updated last month
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆55Sep 17, 2017Updated 8 years ago
- LDPC编码解码matlab代码和Verilog代码及资料☆51Aug 27, 2018Updated 7 years ago
- Playground for implementing LDPC codes on FPGA☆17Jan 1, 2023Updated 3 years ago
- Error Correction Code Transformer☆60Dec 5, 2023Updated 2 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- FPGAandLAN☆29Jun 13, 2021Updated 5 years ago
- Official implementation of "CrossMPT: Cross-attention message-passing transformer for error correcting codes" (ICLR 2025)☆16Feb 1, 2026Updated 6 months ago
- Automatically exported from code.google.com/p/asy4cn☆11Jul 11, 2022Updated 4 years ago
- ☆18Sep 16, 2020Updated 5 years ago
- Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..☆45May 2, 2019Updated 7 years ago
- UDP/IP Core☆12Jul 17, 2014Updated 12 years ago
- Network Tap based on the ZedBoard and Ethernet FMC☆16Jul 7, 2026Updated last month
- ☆13Feb 8, 2021Updated 5 years ago
- Low Density Parity Check codes encoder and decoder, in particular for CCSDS standards.☆68Oct 16, 2018Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- FPGA video scaler running on Intel Arria 10☆12May 28, 2019Updated 7 years ago
- 最小和算法实现☆10Jul 12, 2020Updated 6 years ago
- Solutions to the Google foobar challenges made to me☆12Jun 6, 2022Updated 4 years ago
- Code for paper "NOLD: A Neural-Network Optimized Low-Resolution Decoder for LDPC Codes， Submitted for an IEEE journal;"☆19Apr 14, 2021Updated 5 years ago
- FPGA implementation of an ADAT receiver/transmitter using amaranth HDL☆13Sep 17, 2024Updated last year
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆61Jul 8, 2026Updated last month
- Matlab simulations of the encoder and decoder for the New Radio LDPC code from 3GPP Release 15☆54Mar 11, 2021Updated 5 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆22Oct 31, 2017Updated 8 years ago
- ☆13Mar 9, 2018Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Verilog FPGA code : including experimental DSP audio processor☆14Dec 1, 2020Updated 5 years ago
- fpga for utrasound mobile device☆13Aug 10, 2015Updated 11 years ago
- unsigned Radix-2 SRT division,基2除法☆17May 12, 2015Updated 11 years ago
- RockerIC verification V1 series Labs☆18Mar 24, 2026Updated 4 months ago
- Hardware Description Language Translator☆19Updated this week
- Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. …☆15Jan 19, 2018Updated 8 years ago
- The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)☆10Jan 9, 2016Updated 10 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆21Sep 3, 2019Updated 6 years ago
- RedPitaya application: Software Defined Radio (SDR) for an 8-channel WSPR receiver.☆10Jan 29, 2018Updated 8 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface☆18Dec 23, 2020Updated 5 years ago
- This is a system, whose input is a picture(there may be no license plate, a license plate, or multiple license plates in it), detecting a…☆17Jan 16, 2017Updated 9 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Jul 23, 2020Updated 6 years ago
- Joker TV (USB) FPGA verilog/vhdl code☆16May 19, 2026Updated 2 months ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 12 years ago
- Example Codes for Snorkeling in Verilog Bay☆17Sep 9, 2016Updated 9 years ago
- 4 channel 1GS/s DDS (AD9910 or AD9912 variant)☆19Jul 7, 2025Updated last year