TinyTapeout / tt06-verilog-template
Submission template for Tiny Tapeout 6 - Verilog HDL Projects
☆32Updated 6 months ago
Related projects ⓘ
Alternatives and complementary repositories for tt06-verilog-template
- RISC-V Nox core☆61Updated 3 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆50Updated 2 years ago
- ☆52Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆133Updated 5 months ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆108Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆63Updated 7 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆53Updated 2 weeks ago
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆42Updated 3 weeks ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆62Updated last year
- Simple 8-bit UART realization on Verilog HDL.☆80Updated 6 months ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆45Updated last month
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆98Updated 3 years ago
- ☆10Updated 4 months ago
- Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chil…☆46Updated 2 weeks ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆68Updated 11 months ago
- Summer School Week 1 & 2 repo☆11Updated 2 years ago
- ☆39Updated 2 years ago
- SystemVerilog synthesis tool☆169Updated this week
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆69Updated last year
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆108Updated this week
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 3 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆108Updated this week
- ☆78Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆45Updated 7 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago
- OSVVM Documentation☆30Updated last month
- Learning to do things with the Skywater 130nm process☆72Updated 4 years ago
- UART -> AXI Bridge☆57Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆63Updated 3 years ago