TinyTapeout / tt06-verilog-templateLinks
Submission template for Tiny Tapeout 6 - Verilog HDL Projects
☆34Updated last year
Alternatives and similar repositories for tt06-verilog-template
Users that are interested in tt06-verilog-template are comparing it to the libraries listed below
Sorting:
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆116Updated 4 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated 2 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆71Updated 3 weeks ago
- RISC-V Nox core☆68Updated 2 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆158Updated 2 months ago
- FuseSoC standard core library☆147Updated 4 months ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆56Updated 2 weeks ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆95Updated this week
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆139Updated last month
- Fabric generator and CAD tools.☆198Updated this week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆106Updated 3 weeks ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆110Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆66Updated 3 years ago
- Naive Educational RISC V processor☆88Updated 2 months ago
- SystemVerilog synthesis tool☆209Updated 6 months ago
- My notes for DDR3 SDRAM controller☆39Updated 2 years ago
- Open source ISS and logic RISC-V 32 bit project☆58Updated 3 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆115Updated last month
- ☆53Updated 5 months ago
- SystemVerilog frontend for Yosys☆162Updated this week
- ASIC implementation flow infrastructure☆115Updated last week
- ☆83Updated 2 years ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆86Updated 3 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆110Updated 4 years ago
- ☆43Updated 7 months ago
- ☆108Updated last month