TinyTapeout / tt06-verilog-templateLinks
Submission template for Tiny Tapeout 6 - Verilog HDL Projects
☆34Updated last year
Alternatives and similar repositories for tt06-verilog-template
Users that are interested in tt06-verilog-template are comparing it to the libraries listed below
Sorting:
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆122Updated 3 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆161Updated last month
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆63Updated last month
- ASIC implementation flow infrastructure☆148Updated last week
- RISC-V Nox core☆68Updated 3 months ago
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆100Updated last week
- FuseSoC standard core library☆147Updated 5 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆79Updated 3 weeks ago
- Fabric generator and CAD tools.☆203Updated this week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆149Updated last week
- Verilog digital signal processing components☆158Updated 3 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆117Updated 4 years ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆65Updated last month
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆115Updated last year
- Naive Educational RISC V processor☆91Updated 3 weeks ago
- ☆58Updated 7 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆123Updated 5 years ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆84Updated last week
- Open source ISS and logic RISC-V 32 bit project☆61Updated this week
- Python script to transform a VCD file to wavedrom format☆81Updated 3 years ago
- ☆108Updated 2 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆183Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆116Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 3 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago