TinyTapeout / tt06-verilog-templateLinks
Submission template for Tiny Tapeout 6 - Verilog HDL Projects
☆34Updated last year
Alternatives and similar repositories for tt06-verilog-template
Users that are interested in tt06-verilog-template are comparing it to the libraries listed below
Sorting:
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆61Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆116Updated 4 years ago
- Fabric generator and CAD tools.☆197Updated last week
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆77Updated this week
- ☆54Updated 6 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- Naive Educational RISC V processor☆89Updated last week
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆99Updated this week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆144Updated last week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆158Updated 2 weeks ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆112Updated last year
- RISC-V Nox core☆68Updated 2 months ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- ASIC implementation flow infrastructure☆139Updated this week
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆52Updated last year
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆59Updated last month
- Open source ISS and logic RISC-V 32 bit project☆61Updated 2 weeks ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆107Updated last month
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆47Updated this week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆113Updated 4 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆66Updated 3 years ago
- Flip flop setup, hold & metastability explorer tool☆51Updated 2 years ago
- SystemVerilog frontend for Yosys☆165Updated this week
- ☆84Updated 2 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 11 months ago
- FuseSoC standard core library☆147Updated 4 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- ☆47Updated 2 years ago