TinyTapeout / tt06-verilog-template
Submission template for Tiny Tapeout 6 - Verilog HDL Projects
☆32Updated 8 months ago
Alternatives and similar repositories for tt06-verilog-template:
Users that are interested in tt06-verilog-template are comparing it to the libraries listed below
- RISC-V Nox core☆62Updated 6 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆51Updated 2 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 4 years ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆43Updated this week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆99Updated 3 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆64Updated 4 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆138Updated 7 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆58Updated 2 months ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆109Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 8 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆50Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆65Updated 9 months ago
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆56Updated 2 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆65Updated 2 years ago
- Playing around with Formal Verification of Verilog and VHDL☆54Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆61Updated 2 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆86Updated 4 years ago
- ☆40Updated 2 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆144Updated this week
- Control and status register code generator toolchain☆111Updated last month
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆73Updated this week
- A set of rules and recommendations for analog and digital circuit designers.☆27Updated 2 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆34Updated last week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆46Updated this week
- Curriculum for a university course to teach chip design using open source EDA tools☆57Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆110Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆36Updated 3 years ago