Future-Electronics-Design-Center / Creative-Eval-Board

Related projects ⓘ

Alternatives and complementary repositories for Creative-Eval-Board

• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆37Updated 5 months ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated 11 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆48Updated last week
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆82Updated 6 years ago
• esynr3z / proto245
  🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)
  ☆33Updated 3 years ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆18Updated 9 months ago
• openXC7 / xc7k325t-blinky-nextpnr
  ☆43Updated last year
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆58Updated 5 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆85Updated 4 years ago
• blackmesalabs / s7_mini_fpga
  Example designs for the Spartan7 "S7 Mini" FPGA board
  ☆27Updated 5 years ago
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆48Updated last month
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆20Updated last year
• HarmonInstruments / hififo
  Harmon Instruments FIFO to PCI Express interface
  ☆11Updated 3 years ago
• open-design / riscv-soc-cores
  ☆37Updated 3 years ago
• AngeloJacobo / FPGA_SDRAM_Controller
  SDRAM controller optimized to a memory bandwidth of 316MB/s
  ☆25Updated 3 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆39Updated 3 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 8 years ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆83Updated 8 months ago
• rodrigomelo9 / FOSS-for-FPGAs
  A getting started presentation (with examples) about how to use FLOSS for FPGA development.
  ☆35Updated last year
• mattvenn / first-fpga-pcb
  FPGA dev board based on Lattice iCE40 8k
  ☆65Updated 4 years ago
• plex1 / SpinalDev
  Docker Development Environment for SpinalHDL
  ☆18Updated 3 months ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆30Updated 2 months ago
• olofk / observer
  ☆40Updated 4 years ago
• stnolting / riscv-debug-dtm
  🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
  ☆22Updated last year
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆16Updated 5 years ago
• micro-FPGA / riscv-contest-2018
  RISCV SoftCPU Contest 2018
  ☆14Updated 6 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆64Updated 2 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 2 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆17Updated 5 months ago
• wavedrom / vcd-samples
  sample VCD files
  ☆36Updated 9 months ago