Alternatives and similar repositories for Creative-Eval-Board

Users that are interested in Creative-Eval-Board are comparing it to the libraries listed below

• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆22Updated this week
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆88Updated 6 years ago
• open-design / riscv-soc-cores
  ☆37Updated 4 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆41Updated 4 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆51Updated last week
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 6 years ago
• openXC7 / xc7k325t-blinky-nextpnr
  ☆45Updated 2 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 2 months ago
• stnolting / riscv-debug-dtm
  🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
  ☆26Updated 2 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆63Updated 2 years ago
• blackmesalabs / s7_mini_fpga
  Example designs for the Spartan7 "S7 Mini" FPGA board
  ☆28Updated 6 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆36Updated 6 years ago
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆21Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆46Updated last year
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆28Updated 4 years ago
• openXC7 / demo-projects
  Demo projects for various Kintex FPGA boards
  ☆59Updated 2 weeks ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆90Updated 4 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆24Updated 4 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• lawrie / tiny_usb_examples
  Using the TinyFPGA BX USB code in user designs
  ☆50Updated 6 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• Digilent / Arty-A7
  ☆15Updated 10 months ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆33Updated 4 years ago
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆55Updated 5 months ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆37Updated 4 years ago